end entity scanner;
architecture beh of scanner is
- type SCANNER_STATE is (SINIT, SIDLE, SREAD, STAKE, SDEL, SENTER);
+ type SCANNER_STATE is (SIDLE, SIGNORE_NEXT, SREAD_NEXT, STAKE, SDEL, SENTER);
signal state_int, state_next : SCANNER_STATE;
signal s_char_int, s_char_next : hbyte;
signal s_take_int, s_take_next : std_logic;
signal s_backspace_int, s_backspace_next : std_logic;
signal do_it_int, do_it_next : std_logic;
- signal was_f0_int, was_f0_next : std_logic;
begin
s_char <= s_char_int;
s_take <= s_take_int;
begin
if sys_res_n = '0' then
-- internal
- state_int <= SINIT;
- was_f0_int <= '0';
+ state_int <= SIDLE;
-- out
s_char_int <= (others => '0');
s_take_int <= '0';
elsif rising_edge(sys_clk) then
-- internal
state_int <= state_next;
- was_f0_int <= was_f0_next;
-- out
s_char_int <= s_char_next;
s_take_int <= s_take_next;
end process;
-- next state
- process(state_int, new_data, data, finished, s_done, was_f0_int)
+ process(state_int, new_data, data, finished, s_done)
begin
state_next <= state_int;
case state_int is
- when SINIT =>
- state_next <= SIDLE;
when SIDLE =>
- if new_data = '1' and was_f0_int = '1' then
- state_next <= SREAD;
+ if new_data = '1' then
+ case data is
+ when x"f0" =>
+ state_next <= SIGNORE_NEXT;
+ when x"e0" =>
+ state_next <= SREAD_NEXT;
+ when SC_BKSP =>
+ state_next <= SDEL;
+ when SC_ENTER =>
+ state_next <= SENTER;
+ when SC_KP_0 | SC_KP_1 | SC_KP_2 |
+ SC_KP_3 | SC_KP_4 | SC_KP_5 | SC_KP_6 |
+ SC_KP_7 | SC_KP_8 | SC_KP_9 |
+ SC_0 | SC_1 | SC_2 | SC_3 | SC_4 |
+ SC_5 | SC_6 | SC_7 | SC_8 | SC_9 |
+ SC_PLUS | SC_KP_PLUS |
+ SC_KP_MINUS | SC_KP_MUL | SC_SPACE =>
+ state_next <= STAKE;
+ when others => state_next <= SIDLE;
+ end case;
+ end if;
+ when SIGNORE_NEXT =>
+ if new_data = '1' then
+ state_next <= SIDLE;
+ end if;
+ when SREAD_NEXT =>
+ if new_data = '1' then
+ case data is
+ when x"f0" =>
+ state_next <= SIGNORE_NEXT;
+ when SC_ENTER =>
+ state_next <= SENTER;
+ when SC_KP_DIV =>
+ state_next <= STAKE;
+ when others => state_next <= SIDLE;
+ end case;
end if;
- when SREAD =>
- case data is
- when SC_BKSP => state_next <= SDEL;
- when SC_ENTER => state_next <= SENTER;
- when SC_KP_0 | SC_KP_1 | SC_KP_2 | SC_KP_3 |
- SC_KP_4 | SC_KP_5 | SC_KP_6 | SC_KP_7 |
- SC_KP_8 | SC_KP_9 | SC_KP_PLUS |
- SC_KP_MINUS | SC_KP_MUL | SC_SPACE |
- SC_KP_DIV => state_next <= STAKE;
- when others => state_next <= SIDLE;
- end case;
when STAKE | SDEL=>
if s_done = '1' then
state_next <= SIDLE;
end process;
-- out
- process(state_int, data, s_char_int, new_data, was_f0_int)
+ process(state_int, data, s_char_int, new_data)
function sc2ascii (x : hbyte) return hbyte is
variable y : hbyte;
begin
case x is
- when SC_KP_0 => y := x"30";
- when SC_KP_1 => y := x"31";
- when SC_KP_2 => y := x"32";
- when SC_KP_3 => y := x"33";
- when SC_KP_4 => y := x"34";
- when SC_KP_5 => y := x"35";
- when SC_KP_6 => y := x"36";
- when SC_KP_7 => y := x"37";
- when SC_KP_8 => y := x"38";
- when SC_KP_9 => y := x"39";
- when SC_KP_PLUS => y := x"2b";
+ when SC_KP_0 | SC_0 => y := x"30";
+ when SC_KP_1 | SC_1 => y := x"31";
+ when SC_KP_2 | SC_2 => y := x"32";
+ when SC_KP_3 | SC_3 => y := x"33";
+ when SC_KP_4 | SC_4 => y := x"34";
+ when SC_KP_5 | SC_5 => y := x"35";
+ when SC_KP_6 | SC_6 => y := x"36";
+ when SC_KP_7 | SC_7 => y := x"37";
+ when SC_KP_8 | SC_8 => y := x"38";
+ when SC_KP_9 | SC_9 => y := x"39";
+ when SC_KP_PLUS | SC_PLUS => y := x"2b";
when SC_KP_MINUS => y := x"2d";
when SC_KP_MUL => y := x"2a";
when SC_KP_DIV => y := x"2f";
s_take_next <= '0';
s_backspace_next <= '0';
do_it_next <= '0';
- was_f0_next <= was_f0_int;
case state_int is
- when SINIT =>
- was_f0_next <= '0';
- when SIDLE =>
- if new_data = '1' and data = x"f0" then
- was_f0_next <= '1';
- end if;
- when SREAD =>
- was_f0_next <= '0';
+ when SIDLE => null;
+ when SIGNORE_NEXT => null;
+ when SREAD_NEXT => null;
when STAKE =>
s_take_next <= '1';
s_char_next <= sc2ascii(hbyte(data));
projects / hwmod.git / blobdiff