uart_rx: ein prozessmodell. spart weitere 3 logic elements :P
[hwmod.git] / src / scanner.vhd
index 78a89fa9f82012bdb82bfa33ddcb49250bb34586..1710dc437888bae405c9fe804fcf1827ae4f450d 100644 (file)
@@ -73,9 +73,12 @@ begin
                                                        state_next <= SDEL;
                                                when SC_ENTER =>
                                                        state_next <= SENTER;
-                                               when SC_KP_0 | SC_KP_1 | SC_KP_2 | SC_KP_3 |
-                                                       SC_KP_4 | SC_KP_5 | SC_KP_6 | SC_KP_7 |
-                                                       SC_KP_8 | SC_KP_9 | SC_KP_PLUS |
+                                               when SC_KP_0 | SC_KP_1 | SC_KP_2 |
+                                                       SC_KP_3 | SC_KP_4 | SC_KP_5 | SC_KP_6 |
+                                                       SC_KP_7 | SC_KP_8 | SC_KP_9 |
+                                                       SC_0 | SC_1 | SC_2 | SC_3 | SC_4 |
+                                                       SC_5 | SC_6 | SC_7 | SC_8 | SC_9 |
+                                                       SC_PLUS | SC_KP_PLUS |
                                                        SC_KP_MINUS | SC_KP_MUL | SC_SPACE =>
                                                                state_next <= STAKE;
                                                when others => state_next <= SIDLE;
@@ -114,17 +117,17 @@ begin
                        variable y : hbyte;
                begin
                        case x is
-                               when SC_KP_0 => y := x"30";
-                               when SC_KP_1 => y := x"31";
-                               when SC_KP_2 => y := x"32";
-                               when SC_KP_3 => y := x"33";
-                               when SC_KP_4 => y := x"34";
-                               when SC_KP_5 => y := x"35";
-                               when SC_KP_6 => y := x"36";
-                               when SC_KP_7 => y := x"37";
-                               when SC_KP_8 => y := x"38";
-                               when SC_KP_9 => y := x"39";
-                               when SC_KP_PLUS => y := x"2b";
+                               when SC_KP_0 | SC_0 => y := x"30";
+                               when SC_KP_1 | SC_1 => y := x"31";
+                               when SC_KP_2 | SC_2 => y := x"32";
+                               when SC_KP_3 | SC_3 => y := x"33";
+                               when SC_KP_4 | SC_4 => y := x"34";
+                               when SC_KP_5 | SC_5 => y := x"35";
+                               when SC_KP_6 | SC_6 => y := x"36";
+                               when SC_KP_7 | SC_7 => y := x"37";
+                               when SC_KP_8 | SC_8 => y := x"38";
+                               when SC_KP_9 | SC_9 => y := x"39";
+                               when SC_KP_PLUS | SC_PLUS => y := x"2b";
                                when SC_KP_MINUS => y := x"2d";
                                when SC_KP_MUL => y := x"2a";
                                when SC_KP_DIV => y := x"2f";