uart_rx: ein prozessmodell. spart weitere 3 logic elements :P
[hwmod.git] / src / post_alu_tb.vhd
index b6f9db1899ae1bd6ab88121d18a3d8bb2ea06299..ce4bcc3850df5a5b61cd42e4f72ef395519d6b4e 100644 (file)
@@ -136,6 +136,8 @@ begin
                          61 => (-2147483647, ALU_SUB, 1, 0, -2147483648, false),
                          62 => (-2147483647, ALU_ADD, -1, 0, -2147483648, false),
                          63 => (-2147483648, ALU_DIV, 10, 8, -214748364, false),
+                         64 => (-214748364, ALU_DIV, 10, 4, -21474836, false),
+                         65 => (1, ALU_DIV, -2147483648, 1, 0, false),
                          others => (0, ALU_ADD, 0, 0, 0, false)
                        );
                variable checkall : boolean := true;
@@ -177,14 +179,12 @@ begin
                                        assert(false) report "testfall war ein error (passt)";
                                end if;
                        else
-                               assert op3 = std_logic_vector(to_signed(testmatrix(i).expected,CBITS))
-                                       report "" & cinteger'image(testmatrix(i).o1) & 
+                               if not((op3 = std_logic_vector(to_signed(testmatrix(i).expected,CBITS))) and (opcode /= ALU_DIV or opM = std_logic_vector(to_signed(testmatrix(i).om,CBITS)))) then
+                                       assert(false) report "" & cinteger'image(testmatrix(i).o1) &
                                        " " & integer'image(to_integer(signed(opcode))) &
                                        " " & cinteger'image(testmatrix(i).o2) &
                                        "/= " & integer'image(to_integer(signed(op3))) &
                                        " -- erwartet: " & cinteger'image(testmatrix(i).expected);
-
-                               if not((op3 = std_logic_vector(to_signed(testmatrix(i).expected,CBITS))) and (opM = std_logic_vector(to_signed(testmatrix(i).om,CBITS)))) then
                                        checkall := false;
                                end if;
                        end if;