fixed timing and registers

[hwmod.git] / src / pc_communication.vhd

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index 4e2cc41a0de87b4291976f85c8b4da5b91d24d6f..8c48088e04cc2244664ad986ebd807d109bb2163 100644 (file)
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -17,7 +17,7 @@ entity pc_communication is
                tx_done : in std_logic;
 
                --uart_rx
-               rx_data : in std_logic_vector(7 downto 0); --not really required
+               rx_data : in std_logic_vector(7 downto 0);
                rx_new : in std_logic;
 
                -- History
@@ -32,12 +32,13 @@ end entity pc_communication;
 architecture beh of pc_communication is
        signal push_history, push_history_next : std_logic;
 
-       signal spalte, spalte_next : integer range 1 to 73;
-       signal zeile , zeile_next : integer range 1 to 73;
+       signal spalte, spalte_next : integer range 1 to hspalte_max + 1;
+       signal zeile , zeile_next : integer range 1 to hzeile_max + 1;
        signal spalte_up, spalte_up_next : std_logic;
        signal get, get_next : std_logic;
        signal new_i, new_i_next : std_logic;
        signal tx_done_i, tx_done_i_next : std_logic;
+       signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
        signal d_done_i : std_logic;
        signal s_done, s_done_next : std_logic;
 
@@ -56,6 +57,7 @@ begin
        tx_new <= new_i;
        d_done_i <= d_done;
        tx_done_i_next <= tx_done;
+       tx_data <= tx_data_i;
 
        sync: process (sys_clk, sys_res_n)
        begin
@@ -66,7 +68,7 @@ begin
                        zeile <= 1;
                        get <= '0';
                        new_i <= '0';
-                       tx_data <= "00000000";
+                       tx_data_i <= "00000000";
                        spalte_up <= '0';
                        tx_done_i <= '0';
                        s_done <= '0';
@@ -78,6 +80,7 @@ begin
                        get <= get_next;
                        new_i <= new_i_next;
                        tx_done_i <= tx_done_i_next;
+                       tx_data_i <= tx_data_i_next;
                        spalte_up <= spalte_up_next;
                        s_done <= s_done_next;
                        if (char_en = '1') then
@@ -101,7 +104,7 @@ begin
                end if;
        end process async_push_history;
 
-       output_pc : process (state, zeile, spalte, char, tx_done_i, spalte_up, spalte, zeile)
+       output_pc : process (state, zeile, spalte, char, tx_done_i, spalte_up)
        begin
                get_next <= '0';
                new_i_next <= '0';
@@ -110,14 +113,14 @@ begin
                s_done_next <= '0';
                spalte_next <= spalte;
                zeile_next <= zeile;
+               tx_data_i_next <= tx_data_i;
 
-               if (spalte_up = '1') then
-                       if (spalte > 72) then
-                               if zeile + 1 > 50 then 
+               if spalte_up = '1' then
+                       if spalte = hspalte_max  then
+                               if zeile = hzeile_max then
                                        spalte_next <= 1;
                                        zeile_next <= 1;
-                                       s_done_next <= '1'; --lets assume this false
-                                       --assert false severity failure;
+                                       s_done_next <= '1';
                                else
                                        spalte_next <= 1;
                                        zeile_next <= zeile + 1;
@@ -136,7 +139,7 @@ begin
                                char_en <= '1';
                        when FORWARD =>
                                char_en <= '0';
-                               tx_data <= char;
+                               tx_data_i_next <= char;
                                new_i_next <= '1';
                                if (tx_done_i = '1') then
                                        spalte_up_next <= '1';