fixed timing and registers

[hwmod.git] / src / pc_communication.vhd

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index 4bc09d4c9bd319f745f6a40bd5e9df4071099a93..8c48088e04cc2244664ad986ebd807d109bb2163 100644 (file)
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -17,7 +17,7 @@ entity pc_communication is
                tx_done : in std_logic;
 
                --uart_rx
-               rx_data : in std_logic_vector(7 downto 0); --not really required
+               rx_data : in std_logic_vector(7 downto 0);
                rx_new : in std_logic;
 
                -- History
@@ -32,13 +32,15 @@ end entity pc_communication;
 architecture beh of pc_communication is
        signal push_history, push_history_next : std_logic;
 
-       signal spalte, spalte_next : integer range 0 to 71;
-       signal zeile , zeile_next : integer range 0 to 71;
+       signal spalte, spalte_next : integer range 1 to hspalte_max + 1;
+       signal zeile , zeile_next : integer range 1 to hzeile_max + 1;
        signal spalte_up, spalte_up_next : std_logic;
        signal get, get_next : std_logic;
        signal new_i, new_i_next : std_logic;
        signal tx_done_i, tx_done_i_next : std_logic;
-       signal d_done_i, d_done_i_next : std_logic;
+       signal tx_data_i, tx_data_i_next : std_logic_vector (7 downto 0);
+       signal d_done_i : std_logic;
+       signal s_done, s_done_next : std_logic;
 
        signal char, char_next : hbyte;
        signal char_en : std_logic;
@@ -54,19 +56,22 @@ begin
        char_next <= d_char;
        tx_new <= new_i;
        d_done_i <= d_done;
-       tx_done_i <= tx_done;
+       tx_done_i_next <= tx_done;
+       tx_data <= tx_data_i;
 
        sync: process (sys_clk, sys_res_n)
        begin
                if sys_res_n = '0' then
                        state <= IDLE;
                        push_history <= '0';
-                       spalte <= 0;
-                       zeile <= 0;
+                       spalte <= 1;
+                       zeile <= 1;
                        get <= '0';
                        new_i <= '0';
-                       tx_data <= "00000000";
+                       tx_data_i <= "00000000";
                        spalte_up <= '0';
+                       tx_done_i <= '0';
+                       s_done <= '0';
                elsif rising_edge(sys_clk) then
                        push_history <= push_history_next;
                        spalte <= spalte_next;
@@ -74,29 +79,16 @@ begin
                        state <= state_next;
                        get <= get_next;
                        new_i <= new_i_next;
+                       tx_done_i <= tx_done_i_next;
+                       tx_data_i <= tx_data_i_next;
                        spalte_up <= spalte_up_next;
+                       s_done <= s_done_next;
                        if (char_en = '1') then
                                char <= char_next;
                        end if;
                end if;
        end process sync;
 
-       process (spalte_up, spalte, zeile)
-       begin
-               if (spalte_up = '1') then
-                       if (spalte > 71) then
-                               spalte_next <= 0;
-                               zeile_next <= zeile + 1;
-                       else
-                               spalte_next <= spalte + 1;
-                               zeile_next <= zeile;
-                       end if;
-               else
-                       spalte_next <= spalte;
-                       zeile_next <= zeile;
-               end if;
-       end process;
-
        async_push_history : process (rx_new, rx_data, btn_a)
        begin
                if rx_new = '1' then
@@ -112,11 +104,33 @@ begin
                end if;
        end process async_push_history;
 
-       output_pc : process (state, zeile, spalte, char)
+       output_pc : process (state, zeile, spalte, char, tx_done_i, spalte_up)
        begin
                get_next <= '0';
                new_i_next <= '0';
+
                spalte_up_next <= '0';
+               s_done_next <= '0';
+               spalte_next <= spalte;
+               zeile_next <= zeile;
+               tx_data_i_next <= tx_data_i;
+
+               if spalte_up = '1' then
+                       if spalte = hspalte_max  then
+                               if zeile = hzeile_max then
+                                       spalte_next <= 1;
+                                       zeile_next <= 1;
+                                       s_done_next <= '1';
+                               else
+                                       spalte_next <= 1;
+                                       zeile_next <= zeile + 1;
+                               end if;
+                       else
+                               spalte_next <= spalte + 1; --overflow here!
+                               zeile_next <= zeile;
+                       end if;
+               end if;
+
                case state is
                        when IDLE =>
                                null;
@@ -125,30 +139,32 @@ begin
                                char_en <= '1';
                        when FORWARD =>
                                char_en <= '0';
-                               tx_data <= char;
+                               tx_data_i_next <= char;
                                new_i_next <= '1';
-                               if (tx_done = '1') then
+                               if (tx_done_i = '1') then
                                        spalte_up_next <= '1';
                                end if;
+
                        when DONE =>
                                null;
                end case;
        end process output_pc;
 
-       next_state_pc : process (rx_new, btn_a, d_done, tx_done)
+       next_state_pc : process (rx_new, btn_a, d_done, tx_done_i, s_done)
        begin
                case state is
                        when IDLE =>
                                if rx_new = '1' or btn_a = '1' then
                                        state_next <= FETCH;
-                                       
                                end if;
                        when FETCH =>
                                if (d_done = '1') then
                                        state_next <= FORWARD;
+                               elsif (s_done = '1') then
+                                       state_next <= IDLE;
                                end if;
                        when FORWARD =>
-                               if (tx_done = '1') then
+                               if (tx_done_i = '1') then
                                        state_next <= FETCH;
                                end if;
                        when DONE =>