First working version with beh simulation

[hwmod.git] / src / pc_communication.vhd

diff --git a/src/pc_communication.vhd b/src/pc_communication.vhd
index 4bc09d4c9bd319f745f6a40bd5e9df4071099a93..44e43cdfc0ad6616cc52295ef3d1b299eb635348 100644 (file)
--- a/src/pc_communication.vhd
+++ b/src/pc_communication.vhd
@@ -32,13 +32,13 @@ end entity pc_communication;
 architecture beh of pc_communication is
        signal push_history, push_history_next : std_logic;
 
-       signal spalte, spalte_next : integer range 0 to 71;
-       signal zeile , zeile_next : integer range 0 to 71;
+       signal spalte, spalte_next : integer range 1 to 73;
+       signal zeile , zeile_next : integer range 1 to 73;
        signal spalte_up, spalte_up_next : std_logic;
        signal get, get_next : std_logic;
        signal new_i, new_i_next : std_logic;
        signal tx_done_i, tx_done_i_next : std_logic;
-       signal d_done_i, d_done_i_next : std_logic;
+       signal d_done_i : std_logic;
 
        signal char, char_next : hbyte;
        signal char_en : std_logic;
@@ -54,19 +54,20 @@ begin
        char_next <= d_char;
        tx_new <= new_i;
        d_done_i <= d_done;
-       tx_done_i <= tx_done;
+       tx_done_i_next <= tx_done;
 
        sync: process (sys_clk, sys_res_n)
        begin
                if sys_res_n = '0' then
                        state <= IDLE;
                        push_history <= '0';
-                       spalte <= 0;
-                       zeile <= 0;
+                       spalte <= 1;
+                       zeile <= 1;
                        get <= '0';
                        new_i <= '0';
                        tx_data <= "00000000";
                        spalte_up <= '0';
+                       tx_done_i <= '0';
                elsif rising_edge(sys_clk) then
                        push_history <= push_history_next;
                        spalte <= spalte_next;
@@ -74,6 +75,7 @@ begin
                        state <= state_next;
                        get <= get_next;
                        new_i <= new_i_next;
+                       tx_done_i <= tx_done_i_next;
                        spalte_up <= spalte_up_next;
                        if (char_en = '1') then
                                char <= char_next;
@@ -84,11 +86,18 @@ begin
        process (spalte_up, spalte, zeile)
        begin
                if (spalte_up = '1') then
-                       if (spalte > 71) then
-                               spalte_next <= 0;
-                               zeile_next <= zeile + 1;
+                       if (spalte > 72) then
+                               if zeile + 1 > 50 then 
+                                       spalte_next <= 1;
+                                       zeile_next <= 1;
+                                       --done <= '1'; lets assume this false
+                                       assert false severity failure;
+                               else
+                                       spalte_next <= 1;
+                                       zeile_next <= zeile + 1;
+                               end if;
                        else
-                               spalte_next <= spalte + 1;
+                               spalte_next <= spalte + 1; --overflow here!
                                zeile_next <= zeile;
                        end if;
                else
@@ -112,7 +121,7 @@ begin
                end if;
        end process async_push_history;
 
-       output_pc : process (state, zeile, spalte, char)
+       output_pc : process (state, zeile, spalte, char, tx_done_i)
        begin
                get_next <= '0';
                new_i_next <= '0';
@@ -127,7 +136,7 @@ begin
                                char_en <= '0';
                                tx_data <= char;
                                new_i_next <= '1';
-                               if (tx_done = '1') then
+                               if (tx_done_i = '1') then
                                        spalte_up_next <= '1';
                                end if;
                        when DONE =>
@@ -135,7 +144,7 @@ begin
                end case;
        end process output_pc;
 
-       next_state_pc : process (rx_new, btn_a, d_done, tx_done)
+       next_state_pc : process (rx_new, btn_a, d_done, tx_done_i)
        begin
                case state is
                        when IDLE =>
@@ -148,7 +157,7 @@ begin
                                        state_next <= FORWARD;
                                end if;
                        when FORWARD =>
-                               if (tx_done = '1') then
+                               if (tx_done_i = '1') then
                                        state_next <= FETCH;
                                end if;
                        when DONE =>