signal zeile , zeile_next : hzeile;
signal spalte_up, spalte_up_next : std_logic;
signal get, get_next : std_logic;
+ signal new_i, new_i_next : std_logic;
signal char, char_next : hbyte;
signal char_en : std_logic;
d_zeile <= zeile;
d_spalte <= spalte;
d_get <= get;
+ char_next <= d_char;
+ tx_new <= new_i;
sync: process (sys_clk, sys_res_n)
begin
zeile <= "0000000";
zeile_next <= "0000000";
get <= '0';
- tx_new <= '0';
+ new_i <= '0';
tx_data <= "00000000";
elsif rising_edge(sys_clk) then
push_history <= push_history_next;
zeile <= zeile_next;
state <= state_next;
get <= get_next;
+ new_i <= new_i_next;
if (char_en = '1') then
- state <= state_next;
+ char <= char_next;
end if;
end if;
end process sync;
output_pc : process (state, zeile, spalte, char)
begin
get_next <= '0';
+ new_i_next <= '0';
spalte_next <= "0000000";
zeile_next <= "0000000";
- case state is
+ case state is
when IDLE =>
null;
when FETCH =>
when FORWARD =>
char_en <= '0';
tx_data <= char;
- tx_new <= '1';
+ new_i_next <= '1';
when DONE =>
null;
end case;
when IDLE =>
if rx_new = '1' or btn_a = '1' then
state_next <= FETCH;
- char <= d_char; --latch
+
end if;
when FETCH =>
if (d_done = '1') then