uart_rx: ein prozessmodell. spart weitere 3 logic elements :P
[hwmod.git] / src / parser.vhd
index 5736bf5be96661a7ffa25b678a1f83c121bf86ea..4ad14cc9246a34443f2aa2ebeb710632d5294eaa 100644 (file)
@@ -26,7 +26,7 @@ architecture beh of parser is
                SREAD_SPACE_GET_SIGN, SREAD_SPACE_PROC, SREAD_SPACE_PROC_SIGN, SREAD_OP1, SREAD_OP2,
                SREAD_SIGN, SREAD_NEXTBYTE, SREAD_CALCNUMBER1, SREAD_CALCNUMBER2, SCALC_1,
                SCALC_14, SCALC_15, SCALC_2, SWRITE_CHAR0, SWRITE_CHAR1, SWRITE_CHAR2,
-               SWRITE_SIGN1, SWRITE_SIGN2, SDONE, SERROR1, SERROR2);
+               SWRITE_SIGN1, SWRITE_SIGN2, SDONE, SERROR1, SERROR2, SBLANK1, SBLANK2);
        signal state_int, state_next : PARSER_STATE;
        signal z_int, z_next, strich_int, strich_next, wtmp_int, wtmp_next : csigned;
        signal punkt_int, punkt_next : csigned;
@@ -46,7 +46,6 @@ architecture beh of parser is
        signal firstz_next, firstz_int : boolean;
        signal err_next, err_int : hstr_int;
        signal errc_next, errc_int : hstr_int;
-       signal errc_tmp_next, errc_tmp_int : hstr_int;
        -- ALU
        signal opcode : alu_ops;
        signal op1 : csigned;
@@ -57,9 +56,8 @@ architecture beh of parser is
        signal calc_done : std_logic;
        signal calc_error : std_logic;
 begin
-       instalu : entity work.alu(beh)
-       port map
-       (
+       instalu : alu
+       port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
                do_calc => do_calc,
@@ -97,7 +95,6 @@ begin
                        opp_int <= ALU_NOP;
                        err_int <= 0;
                        errc_int <= HSPALTE_MAX;
-                       errc_tmp_int <= 0;
                        firstz_int <= true;
                        -- out ports
                        p_rget_int <= '0';
@@ -122,7 +119,6 @@ begin
                        opp_int <= opp_next;
                        err_int <= err_next;
                        errc_int <= errc_next;
-                       errc_tmp_int <= errc_tmp_next;
                        firstz_int <= firstz_next;
                        -- out ports
                        p_rget_int <= p_rget_next;
@@ -142,7 +138,7 @@ begin
                        calc_done, wtmp_int, opp_int, z_sign_int, err_int, errc_int,
                        calc_error, op2_int, state_int, p_write_int, z_int, rbyte_int,
                        p_rget_int, opcode_int, op1_int, op3, opM, do_calc_int,
-                       errc_tmp_int, firstz_int)
+                       firstz_int)
                function hbyte2csigned (x : hbyte) return csigned is
                        variable y : csigned;
                begin
@@ -203,7 +199,6 @@ begin
                opp_next <= opp_int;
                err_next <= err_int;
                errc_next <= errc_int;
-               errc_tmp_next <= errc_tmp_int;
                firstz_next <= firstz_int;
                -- signals
                p_rget_next <= '0';
@@ -455,13 +450,14 @@ begin
                                wtmp_next <= op3;
 
                                if p_wdone = '1' then
+                                       errc_next <= errc_int - 1;
                                        -- ueberpruefung auf -2147483648 fuer testfall 39 und 40
                                        -- x"80000000": xst (xilinx) workaround
                                        if strich_int < 10 and strich_int /= x"80000000" then
                                                if z_sign_int = '1' then
                                                        state_next <= SWRITE_SIGN1;
                                                else
-                                                       state_next <= SDONE;
+                                                       state_next <= SBLANK1;
                                                end if;
                                        else
                                                state_next <= SWRITE_CHAR2;
@@ -486,14 +482,31 @@ begin
                                end if;
 
                                if p_wdone = '1' then
+                                       errc_next <= errc_int - 1;
                                        state_next <= SDONE;
                                end if;
 
+                       when SBLANK1 =>
+                               p_wtake_next <= '1';
+                               p_write_next <= x"20";
+                               if p_wdone = '1' then
+                                       errc_next <= errc_int - 1;
+                                       if errc_int <= 2 then
+                                               state_next <= SDONE;
+                                       else
+                                               state_next <= SBLANK2;
+                                       end if;
+                               end if;
+                       when SBLANK2 =>
+                               if p_wdone = '0' then
+                                       state_next <= SBLANK1;
+                               end if;
+
                        when SERROR1 =>
                                p_wtake_next <= '1';
                                p_write_next <= hbyte(to_unsigned (character'pos(error_str(err_int)(errc_int)),8));
-                               errc_tmp_next <= errc_int - 1;
                                if p_wdone = '1' then
+                                       errc_next <= errc_int - 1;
                                        if errc_int <= 2 then
                                                state_next <= SDONE;
                                        else
@@ -501,7 +514,6 @@ begin
                                        end if;
                                end if;
                        when SERROR2 =>
-                               errc_next <= errc_tmp_int;
                                if p_wdone = '0' then
                                        state_next <= SERROR1;
                                end if;