architecture beh of history is
type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE,
- S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_READ);
+ S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1, S_PC_INIT, S_PC_DUMMY ,S_PC_READ);
signal state_int, state_next : HISTORY_STATE;
signal was_bs_int, was_bs_next : std_logic;
signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
state_next <= SIDLE;
end if;
when S_PC_INIT =>
+ state_next <= S_PC_DUMMY;
+ when S_PC_DUMMY =>
state_next <= S_PC_READ;
when S_PC_READ =>
- if d_get = '0' then
+ if pc_get = '0' then
state_next <= SIDLE;
end if;
when S_P_READ =>
address_next <= address_int;
data_in_next <= data_in_int;
pc_done_next <= '0';
- pc_char_next <= pc_char_int; --(others => '0');
+ pc_char_next <= pc_char_int;
pc_busy_next <= '0';
p_rdone_next <= p_rdone_int;
p_wdone_next <= p_wdone_int;
addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(pc_spalte));
address_next <= addr_tmp;
pc_busy_next <= '1';
+ when S_PC_DUMMY =>
+ pc_busy_next <= '1';
when S_PC_READ =>
pc_char_next <= data_out;
pc_done_next <= '1';