history/display: nach d_new_result = '1' werden die naechsten 70 bytes vom display

[hwmod.git] / src / history.vhd

diff --git a/src/history.vhd b/src/history.vhd
index 76c4bf70bec70ce1bda69440fa83136f5576ec86..ca9800f1dd5140b7307e936523f460a52fd30e67 100644 (file)
--- a/src/history.vhd
+++ b/src/history.vhd
@@ -34,9 +34,10 @@ end entity history;
 
 architecture beh of history is
        type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
-               S_D_INIT, S_D_WRITE);
+               S_D_INIT, S_D_READ, S_S_FIN_POSUP);
        signal state_int, state_next : HISTORY_STATE;
        signal was_bs_int, was_bs_next : std_logic;
+       signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
        signal s_done_int, s_done_next : std_logic;
        signal s_cnt_int, s_cnt_next : hspalte;
        signal d_new_eingabe_int, d_new_eingabe_next : std_logic;
@@ -67,6 +68,7 @@ begin
                        -- internal
                        state_int <= SIDLE;
                        was_bs_int <= '0';
+                       pos_int <= (others => '0');
                        -- out
                        s_done_int <= '0';
                        s_cnt_int <= (0 => '1', others => '0');
@@ -85,6 +87,7 @@ begin
                        -- internal
                        state_int <= state_next;
                        was_bs_int <= was_bs_next;
+                       pos_int <= pos_next;
                        -- out
                        s_done_int <= s_done_next;
                        s_cnt_int <= s_cnt_next;
@@ -129,16 +132,18 @@ begin
                                state_next <= S_S_DONE;
                        when S_S_FIN =>
                                if do_it = '0' then
-                                       state_next <= SIDLE;
+                                       state_next <= S_S_FIN_POSUP;
                                end if;
+                       when S_S_FIN_POSUP =>
+                               state_next <= SIDLE;
                        when S_S_DONE =>
                                if s_take = '0' then
                                        state_next <= SIDLE;
                                end if;
 
                        when S_D_INIT =>
-                               state_next <= S_D_WRITE;
-                       when S_D_WRITE =>
+                               state_next <= S_D_READ;
+                       when S_D_READ =>
                                if d_get = '0' then
                                        state_next <= SIDLE;
                                end if;
@@ -146,14 +151,16 @@ begin
        end process;
 
        -- out
-       process(state_int, s_cnt_int, d_spalte, data_out, s_char, address_int,
+       process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int,
                data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int,
-               was_bs_int, s_take)
+               was_bs_int, s_take, pos_int)
                variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
+               variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0);
        begin
                s_done_next <= '0';
                s_cnt_next <= s_cnt_int;
                was_bs_next <= was_bs_int;
+               pos_next <= pos_int;
                d_new_result_next <= d_new_result_int;
                d_new_eingabe_next <= d_new_eingabe_int;
                d_new_bs_next <= '0';
@@ -175,7 +182,7 @@ begin
                                -- TODO: '/=' billiger als '<' ?
                                if unsigned(s_cnt_int) /= 71 then
                                        wr_next <= '1';
-                                       address_next <= s_cnt_int;
+                                       address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
                                        data_in_next <= s_char;
                                        s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
                                else
@@ -184,22 +191,26 @@ begin
                                end if;
                        when S_S_BS =>
                                -- ab 1 darf nicht mehr dekrementiert werden
+                               addr_tmp := (others => '0');
                                if unsigned(s_cnt_int) /= 1 then
-                                       addr_tmp := std_logic_vector(unsigned(s_cnt_int) - 1);
+                                       addr_tmp(hspalte'length - 1 downto 0) := std_logic_vector(unsigned(s_cnt_int) - 1);
                                        d_new_bs_next <= '1';
                                else
-                                       addr_tmp := s_cnt_int;
+                                       addr_tmp(hspalte'length - 1 downto 0) := s_cnt_int;
                                end if;
-                               s_cnt_next <= addr_tmp;
+                               s_cnt_next <= addr_tmp(hspalte'length - 1 downto 0);
                
                                wr_next <= '1';
-                               address_next <= addr_tmp;
+                               address_next <= std_logic_vector(unsigned(pos_int) + unsigned(addr_tmp));
                                data_in_next <= (others => '0');
                                was_bs_next <= '1';
                        when S_S_FIN =>
                                finished_next <= '1';
                                s_cnt_next <= (0 => '1', others => '0');
                                d_new_result_next <= '1';
+                       when S_S_FIN_POSUP =>
+                               -- TODO: overflow nach 50 berechnungen... => wieder von vorne anfangen
+                               pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH));
                        when S_S_DONE =>
                                s_done_next <= '1';
                                if was_bs_int = '0' then
@@ -210,10 +221,15 @@ begin
                                end if;
 
                        when S_D_INIT =>
-                               address_next <= d_spalte;
+                               addr_tmp := (others => '0');
+                               addr_tmp(hzeile'length - 1 downto 0) := d_zeile;
+                               mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH));
+                               addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
+                               addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte));
+                               address_next <= addr_tmp;
                                d_new_eingabe_next <= '0';
                                d_new_result_next <= '0';
-                       when S_D_WRITE =>
+                       when S_D_READ =>
                                d_char_next <= data_out;
                                d_done_next <= '1';
                end case;