history: clear ram on reset

[hwmod.git] / src / history.vhd

diff --git a/src/history.vhd b/src/history.vhd
index cf091e317b9aeafcef64a464e8a4f25d012d3e2b..9a65e590e4071023efebb1f6e80ccb5f25b78aab 100644 (file)
--- a/src/history.vhd
+++ b/src/history.vhd
@@ -37,7 +37,7 @@ end entity history;
 architecture beh of history is
        type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
                S_D_INIT, S_D_READ, S_S_FIN_POSUP, S_P_READ, S_P_READ_DONE, S_P_WRITE,
-               S_P_WRITE_DONE, S_P_DONE);
+               S_P_WRITE_DONE, S_P_DONE, S_INIT, S_S_CLEAR_NEXT0, S_S_CLEAR_NEXT1);
        signal state_int, state_next : HISTORY_STATE;
        signal was_bs_int, was_bs_next : std_logic;
        signal pos_int, pos_next : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
@@ -73,7 +73,7 @@ begin
        begin
                if sys_res_n = '0' then
                        -- internal
-                       state_int <= SIDLE;
+                       state_int <= S_INIT;
                        was_bs_int <= '0';
                        pos_int <= (others => '0');
                        -- out
@@ -120,11 +120,17 @@ begin
 
        -- next state
        process(state_int, d_get, p_finished, s_take, s_backspace, was_bs_int,
-               p_rget, p_wtake)
+               p_rget, p_wtake, pos_int, s_cnt_int)
        begin
                state_next <= state_int;
 
                case state_int is
+                       when S_INIT =>
+                               -- ganzen speicher clearen: fuer ausgabe am vga nicht umbedingt
+                               -- noetig, aber spaetestens fuers dumpen per rs232
+                               if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then
+                                       state_next <= SIDLE;
+                               end if;
                        when SIDLE =>
                                -- S_S_FIN: tmp..
                                if s_take = '1' then
@@ -153,7 +159,15 @@ begin
                                        state_next <= S_S_FIN_POSUP;
                                end if;
                        when S_S_FIN_POSUP =>
-                               state_next <= SIDLE;
+                               state_next <= S_S_CLEAR_NEXT0;
+                       when S_S_CLEAR_NEXT0 =>
+                               if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
+                                       state_next <= S_S_CLEAR_NEXT1;
+                               end if;
+                       when S_S_CLEAR_NEXT1 =>
+                               if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
+                                       state_next <= SIDLE;
+                               end if;
                        when S_S_DONE =>
                                if s_take = '0' then
                                        state_next <= SIDLE;
@@ -211,6 +225,15 @@ begin
                p_sp_write_next <= p_sp_write_int;
 
                case state_int is
+                       when S_INIT =>
+                               wr_next <= '1';
+                               address_next <= pos_int;
+                               data_in_next <= (others => '0');
+                               if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE,H_RAM_WIDTH)) then
+                                       pos_next <= (others => '0');
+                               else
+                                       pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(1,H_RAM_WIDTH));
+                               end if;
                        when SIDLE =>
                                -- TODO: tmp fix
                                d_new_result_next <= '0';
@@ -250,8 +273,32 @@ begin
                                p_sp_read_next <= (others => '0');
                                p_sp_write_next <= std_logic_vector(to_unsigned(71,p_sp_write_next'length));
                        when S_S_FIN_POSUP =>
-                               -- TODO: overflow nach 50 berechnungen... => wieder von vorne anfangen
-                               pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH));
+                               -- overflowcheck nach 50 berechnungen => wieder von vorne anfangen
+                               if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE-142,H_RAM_WIDTH)) then
+                                       pos_next <= (others => '0');
+                               else
+                                       pos_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(142,H_RAM_WIDTH));
+                               end if;
+                       when S_S_CLEAR_NEXT0 =>
+                               -- die naechsten 142 bytes im speicher resetten
+                               wr_next <= '1';
+                               address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
+                               data_in_next <= (others => '0');
+                               if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
+                                       s_cnt_next <= (0 => '1', others => '0');
+                               else
+                                       s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
+                               end if;
+                       when S_S_CLEAR_NEXT1 =>
+                               -- die naechsten 142 bytes im speicher resetten
+                               wr_next <= '1';
+                               address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(s_cnt_int));
+                               data_in_next <= (others => '0');
+                               if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
+                                       s_cnt_next <= (0 => '1', others => '0');
+                               else
+                                       s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
+                               end if;
                        when S_S_DONE =>
                                s_done_next <= '1';
                                if was_bs_int = '0' then