history: simple implementierung + testbench

[hwmod.git] / src / history.vhd

diff --git a/src/history.vhd b/src/history.vhd
index fc0abbe65df10f9664c630e691b493e3e77db1e9..2f3c2dd0334bd8986e53fa2464c846b673d77859 100644 (file)
--- a/src/history.vhd
+++ b/src/history.vhd
@@ -32,9 +32,11 @@ entity history is
 end entity history;
 
 architecture beh of history is
-       type HISTORY_STATE is (SIDLE);
+       type HISTORY_STATE is (SIDLE, S_S_INIT, S_S_WRITE, S_S_BS, S_S_DONE, S_S_FIN,
+               S_D_INIT, S_D_WAIT, S_D_WRITE);
        signal state_int, state_next : HISTORY_STATE;
        signal s_done_int, s_done_next : std_logic;
+       signal s_cnt_int, s_cnt_next : hspalte;
        signal d_new_eingabe_int, d_new_eingabe_next : std_logic;
        signal d_new_result_int, d_new_result_next : std_logic;
        signal d_done_int, d_done_next : std_logic;
@@ -43,9 +45,9 @@ architecture beh of history is
        signal finished_int, finished_next : std_logic;
 
        -- ram
-       signal address, address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
-       signal data_out, data_in, data_in_next, data_in_int : hbyte;
-       signal wr, wr_next, wr_int : std_logic;
+       signal address_next, address_int : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
+       signal data_out, data_in_next, data_in_int : hbyte;
+       signal wr_next, wr_int : std_logic;
 begin
        s_done <= s_done_int;
        d_new_eingabe <= d_new_eingabe_int;
@@ -55,10 +57,6 @@ begin
 
        finished <= finished_int;
 
-       address <= address_int;
-       data_in <= data_in_int;
-       wr <= wr_int;
-
        process(sys_clk, sys_res_n)
        begin
                if sys_res_n = '0' then
@@ -66,6 +64,7 @@ begin
                        state_int <= SIDLE;
                        -- out
                        s_done_int <= '0';
+                       s_cnt_int <= (0 => '1', others => '0');
                        d_new_result_int <= '0';
                        d_new_eingabe_int <= '0';
                        d_done_int <= '0';
@@ -73,7 +72,7 @@ begin
 
                        finished_int <= '0';
 
-                       address_int <= (others => '0');
+                       address_int <= (0 => '1', others => '0');
                        data_in_int <= x"00";
                        wr_int <= '0';
                elsif rising_edge(sys_clk) then
@@ -81,6 +80,7 @@ begin
                        state_int <= state_next;
                        -- out
                        s_done_int <= s_done_next;
+                       s_cnt_int <= s_cnt_next;
                        d_new_result_int <= d_new_result_next;
                        d_new_eingabe_int <= d_new_eingabe_next;
                        d_done_int <= d_done_next;
@@ -95,22 +95,93 @@ begin
        end process;
 
        -- next state
-       process(state_int)
+       process(state_int, d_get, do_it, s_take, s_backspace)
        begin
                state_next <= state_int;
 
                case state_int is
                        when SIDLE =>
-                               null;
+                               -- S_S_FIN: tmp..
+                               if d_get = '1' then
+                                       state_next <= S_D_INIT;
+                               elsif do_it = '1' then
+                                       state_next <= S_S_FIN;
+                               elsif s_take = '1' then
+                                       state_next <= S_S_INIT;
+                               end if;
+                       when S_S_INIT =>
+                               if s_backspace = '1' then
+                                       state_next <= S_S_BS;
+                               else
+                                       state_next <= S_S_WRITE;
+                               end if;
+                       when S_S_WRITE | S_S_BS =>
+                               state_next <= S_S_DONE;
+                       when S_S_FIN =>
+                               if do_it = '0' then
+                                       state_next <= SIDLE;
+                               end if;
+                       when S_S_DONE =>
+                               if s_take = '0' then
+                                       state_next <= SIDLE;
+                               end if;
+
+                       when S_D_INIT =>
+                               state_next <= S_D_WAIT;
+                       when S_D_WAIT =>
+                               state_next <= S_D_WRITE;
+                       when S_D_WRITE =>
+                               if d_get = '0' then
+                                       state_next <= SIDLE;
+                               end if;
                end case;
        end process;
 
        -- out
-       process(state_int)
+       process(state_int, s_cnt_int, d_spalte, data_out, s_char, address_int,
+               data_in_int)
        begin
+               s_done_next <= '0';
+               s_cnt_next <= s_cnt_int;
+               d_new_result_next <= '0';
+               d_new_eingabe_next <= '0';
+               d_done_next <= '0';
+               d_char_next <= (others => '0');
+               finished_next <= '0';
+               wr_next <= '0';
+               address_next <= address_int;
+               data_in_next <= data_in_int;
+
                case state_int is
                        when SIDLE =>
                                null;
+                       when S_S_INIT =>
+                               null;
+                       when S_S_WRITE =>
+                               wr_next <= '1';
+                               address_next <= '0' & s_cnt_int;
+                               data_in_next <= s_char;
+                               s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
+                       when S_S_BS =>
+                               wr_next <= '1';
+                               address_next <= '0' & std_logic_vector(unsigned(s_cnt_int) - 1);
+                               data_in_next <= (others => '0');
+                               s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) - 1);
+                       when S_S_FIN =>
+                               finished_next <= '1';
+                               s_cnt_next <= (0 => '1', others => '0');
+                               d_new_result_next <= '1';
+                       when S_S_DONE =>
+                               s_done_next <= '1';
+                               d_new_eingabe_next <= '1';
+
+                       when S_D_INIT =>
+                               address_next <= '0' & d_spalte;
+                       when S_D_WAIT =>
+                               null;
+                       when S_D_WRITE =>
+                               d_char_next <= data_out;
+                               d_done_next <= '1';
                end case;
        end process;
 
@@ -120,10 +191,9 @@ begin
        )
        port map (
                sys_clk => sys_clk,
-               sys_res_n => sys_res_n,
-               address => address,
+               address => address_int,
                data_out => data_out,
-               wr => wr,
-               data_in => data_in
+               wr => wr_int,
+               data_in => data_in_int
        );
 end architecture beh;