display/history: komisches init verhalten
[hwmod.git] / src / history.vhd
index c9f56569de863af75217b29fb36f012542daf21f..1c69612edb72fd9c0a72091890433600cbae353e 100644 (file)
@@ -102,12 +102,12 @@ begin
                case state_int is
                        when SIDLE =>
                                -- S_S_FIN: tmp..
-                               if d_get = '1' then
-                                       state_next <= S_D_INIT;
+                               if s_take = '1' then
+                                       state_next <= S_S_INIT;
                                elsif do_it = '1' then
                                        state_next <= S_S_FIN;
-                               elsif s_take = '1' then
-                                       state_next <= S_S_INIT;
+                               elsif d_get = '1' then
+                                       state_next <= S_D_INIT;
                                end if;
                        when S_S_INIT =>
                                if s_backspace = '1' then
@@ -158,13 +158,13 @@ begin
                        when S_S_INIT =>
                                null;
                        when S_S_WRITE =>
-                               -- wr_next <= '1';
-                               address_next <= '0' & s_cnt_int;
+                               wr_next <= '1';
+                               address_next <= s_cnt_int;
                                data_in_next <= s_char;
                                s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
                        when S_S_BS =>
-                               -- wr_next <= '1';
-                               address_next <= '0' & std_logic_vector(unsigned(s_cnt_int) - 1);
+                               wr_next <= '1';
+                               address_next <= std_logic_vector(unsigned(s_cnt_int) - 1);
                                data_in_next <= (others => '0');
                                if unsigned(s_cnt_int) /= 0 then
                                        s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) - 1);
@@ -178,7 +178,7 @@ begin
                                d_new_eingabe_next <= '1';
 
                        when S_D_INIT =>
-                               address_next <= '0' & d_spalte;
+                               address_next <= d_spalte;
                                d_new_eingabe_next <= '0';
                                d_new_result_next <= '0';
                        when S_D_WAIT =>