uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / history.vhd

diff --git a/src/history.vhd b/src/history.vhd
index 1cac445f7fccfe7054ac2de54c4b37654b64fcdc..0c918687d73c07d569e9ef03b9cf7793042d9cf0 100644 (file)
--- a/src/history.vhd
+++ b/src/history.vhd
@@ -74,6 +74,8 @@ begin
        p_rdone <= p_rdone_int;
        p_wdone <= p_wdone_int;
        p_read <= p_read_int;
+       pc_done <= pc_done_int;
+       pc_char <= pc_char_int;
 
        process(sys_clk, sys_res_n)
        begin
@@ -94,7 +96,7 @@ begin
                        p_wdone_int <= '0';
                        p_read_int <= (others => '0');
                        p_sp_read_int <= (others => '0');
-                       p_sp_write_int <= std_logic_vector(to_unsigned(71,p_sp_write_int'length));
+                       p_sp_write_int <= std_logic_vector(to_unsigned(HSPALTE_MAX,p_sp_write_int'length));
 
                        pc_char_int  <= (others => '0');
                        pc_done_int  <= '0';
@@ -175,11 +177,11 @@ begin
                        when S_S_FIN_POSUP =>
                                state_next <= S_S_CLEAR_NEXT0;
                        when S_S_CLEAR_NEXT0 =>
-                               if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
+                               if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then
                                        state_next <= S_S_CLEAR_NEXT1;
                                end if;
                        when S_S_CLEAR_NEXT1 =>
-                               if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
+                               if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then
                                        state_next <= SIDLE;
                                end if;
                        when S_S_DONE =>
@@ -196,7 +198,7 @@ begin
                        when S_PC_INIT =>
                                state_next <= S_PC_READ;
                        when S_PC_READ =>
-                               if d_get = '0' then
+                               if pc_get = '0' then
                                        state_next <= SIDLE;
                                end if;
                        when S_P_READ =>
@@ -220,7 +222,7 @@ begin
        process(state_int, s_cnt_int, d_spalte, d_zeile, data_out, s_char, address_int,
                        data_in_int, d_new_result_int, d_new_eingabe_int, d_new_bs_int,
                        was_bs_int, s_take, pos_int, p_rdone_int, p_wdone_int, p_read_int,
-                       p_write, p_sp_read_int, p_sp_write_int)
+                       p_write, p_sp_read_int, p_sp_write_int, pc_char_int, pc_zeile, pc_spalte)
                variable addr_tmp : std_logic_vector(H_RAM_WIDTH - 1 downto 0);
                variable spalte_tmp : hspalte;
                variable mul_tmp : std_logic_vector((H_RAM_WIDTH*2) -1 downto 0);
@@ -237,8 +239,8 @@ begin
                wr_next <= '0';
                address_next <= address_int;
                data_in_next <= data_in_int;
-               pc_done <= '0';
-               pc_char <= (others => '0');
+               pc_done_next <= '0';
+               pc_char_next <= pc_char_int;
                p_rdone_next <= p_rdone_int;
                p_wdone_next <= p_wdone_int;
                p_read_next <= p_read_int;
@@ -260,9 +262,9 @@ begin
                        when S_S_INIT =>
                                null;
                        when S_S_WRITE =>
-                               -- nur bei < 71 weiter machen
+                               -- nur bei < HSPALTE_MAX weiter machen
                                -- Hint: '/=' billiger als '<'
-                               if unsigned(s_cnt_int) /= 71 then
+                               if unsigned(s_cnt_int) /= HSPALTE_MAX then
                                        wr_next <= '1';
                                        address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
                                        data_in_next <= s_char;
@@ -281,7 +283,6 @@ begin
                                        addr_tmp(hspalte'length - 1 downto 0) := s_cnt_int;
                                end if;
                                s_cnt_next <= addr_tmp(hspalte'length - 1 downto 0);
-               
                                wr_next <= '1';
                                address_next <= std_logic_vector(unsigned(pos_int) + unsigned(addr_tmp));
                                data_in_next <= (others => '0');
@@ -291,7 +292,7 @@ begin
                                d_new_result_next <= '1';
                                -- resetten der parser counter
                                p_sp_read_next <= (others => '0');
-                               p_sp_write_next <= std_logic_vector(to_unsigned(71,p_sp_write_next'length));
+                               p_sp_write_next <= std_logic_vector(to_unsigned(HSPALTE_MAX,p_sp_write_next'length));
                        when S_S_FIN_POSUP =>
                                -- overflowcheck nach 50 berechnungen => wieder von vorne anfangen
                                if pos_int = std_logic_vector(to_unsigned(H_RAM_SIZE-142,H_RAM_WIDTH)) then
@@ -304,7 +305,7 @@ begin
                                wr_next <= '1';
                                address_next <= std_logic_vector(unsigned(pos_int) + unsigned(s_cnt_int));
                                data_in_next <= (others => '0');
-                               if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
+                               if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then
                                        s_cnt_next <= (0 => '1', others => '0');
                                else
                                        s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
@@ -312,9 +313,9 @@ begin
                        when S_S_CLEAR_NEXT1 =>
                                -- die naechsten 142 bytes im speicher resetten
                                wr_next <= '1';
-                               address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(s_cnt_int));
+                               address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(HSPALTE_MAX,H_RAM_WIDTH) + unsigned(s_cnt_int));
                                data_in_next <= (others => '0');
-                               if s_cnt_int = hspalte(to_unsigned(71,hspalte'length)) then
+                               if s_cnt_int = hspalte(to_unsigned(HSPALTE_MAX,hspalte'length)) then
                                        s_cnt_next <= (0 => '1', others => '0');
                                else
                                        s_cnt_next <= std_logic_vector(unsigned(s_cnt_int) + 1);
@@ -331,7 +332,7 @@ begin
                        when S_D_INIT =>
                                addr_tmp := (others => '0');
                                addr_tmp(hzeile'length - 1 downto 0) := d_zeile;
-                               mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH));
+                               mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(HSPALTE_MAX,H_RAM_WIDTH));
                                addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
                                addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(d_spalte));
                                address_next <= addr_tmp;
@@ -344,13 +345,14 @@ begin
                        when S_PC_INIT =>
                                addr_tmp := (others => '0');
                                addr_tmp(hzeile'length - 1 downto 0) := pc_zeile;
-                               mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(71,H_RAM_WIDTH));
+                               mul_tmp := std_logic_vector(unsigned(addr_tmp) * to_unsigned(HSPALTE_MAX,H_RAM_WIDTH));
                                addr_tmp := mul_tmp((addr_tmp'length - 1) downto 0);
                                addr_tmp := std_logic_vector(unsigned(addr_tmp) + unsigned(pc_spalte));
                                address_next <= addr_tmp;
                        when S_PC_READ =>
-                               pc_char_next <= data_out;
                                pc_done_next <= '1';
+                               pc_char_next <= data_out;
+
                        when S_P_READ =>
                                wr_next <= '0';
                                spalte_tmp := std_logic_vector(unsigned(p_sp_read_int) + 1);
@@ -365,7 +367,7 @@ begin
                                data_in_next <= p_write;
                                spalte_tmp := std_logic_vector(unsigned(p_sp_write_int) - 1);
                                p_sp_write_next <= spalte_tmp;
-                               address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(71,H_RAM_WIDTH) + unsigned(spalte_tmp));
+                               address_next <= std_logic_vector(unsigned(pos_int) + to_unsigned(HSPALTE_MAX,H_RAM_WIDTH) + unsigned(spalte_tmp));
                        when S_P_WRITE_DONE =>
                                p_wdone_next <= '1';
                        when S_P_DONE =>
@@ -374,7 +376,7 @@ begin
                end case;
        end process;
 
-       sp_ram_inst : entity work.sp_ram(beh)
+       sp_ram_inst : sp_ram
        generic map (
                ADDR_WIDTH => H_RAM_WIDTH
        )