alu: refactor von drei prozessmodell auf zwei prozessmodell

[hwmod.git] / src / gen_pkg.vhd

diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd
index cb87dbab6d977aed99c2750d5559556f4b7fc850..d97b94350ac47ac3d0dc1492805ea44497df84cb 100644 (file)
--- a/src/gen_pkg.vhd
+++ b/src/gen_pkg.vhd
@@ -1,9 +1,75 @@
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
+use work.math_pkg.all;
 
 package gen_pkg is
-       type alu_ops is (NOP, SUB, ADD, MUL, DIV, DONE);
-       subtype csigned is signed(31 downto 0);
+       subtype alu_ops is std_logic_vector(2 downto 0);
+       constant ALU_NOP : alu_ops := "000";
+       constant ALU_SUB : alu_ops := "001";
+       constant ALU_ADD : alu_ops := "010";
+       constant ALU_MUL : alu_ops := "011";
+       constant ALU_DIV : alu_ops := "100";
+       constant ALU_DONE : alu_ops := "101";
+
+       constant CBITS : integer := 32;
+       subtype csigned is signed((CBITS-1) downto 0);
+       subtype divinteger is unsigned(4 downto 0);
+       -- integer ist 32bit (31bit + sign)
+       subtype cinteger is integer;
+
+       -- 50 zeilen * 71 zeichen * 2 (berechnung + ergebnis) = 7100 bytes
+       constant H_RAM_SIZE : integer := 7100;
+       constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE);
+       subtype hspalte is std_logic_vector(6 downto 0);
+       subtype hzeile is std_logic_vector(6 downto 0);
+       subtype hbyte is std_logic_vector(7 downto 0);
+       subtype hstring is string(1 to 72);
+       subtype hstr_int is integer range 0 to 72;
+
+       procedure icwait(signal clk_i : IN std_logic; cycles: natural);
+
+       -- http://www.marjorie.de/ps2/scancode-set2.htm
+       constant SC_KP_0 : std_logic_vector(7 downto 0) := x"70";
+       constant SC_KP_1 : std_logic_vector(7 downto 0) := x"69";
+       constant SC_KP_2 : std_logic_vector(7 downto 0) := x"72";
+       constant SC_KP_3 : std_logic_vector(7 downto 0) := x"7a";
+       constant SC_KP_4 : std_logic_vector(7 downto 0) := x"6b";
+       constant SC_KP_5 : std_logic_vector(7 downto 0) := x"73";
+       constant SC_KP_6 : std_logic_vector(7 downto 0) := x"74";
+       constant SC_KP_7 : std_logic_vector(7 downto 0) := x"6c";
+       constant SC_KP_8 : std_logic_vector(7 downto 0) := x"75";
+       constant SC_KP_9 : std_logic_vector(7 downto 0) := x"7d";
+
+       constant SC_0 : std_logic_vector(7 downto 0) := x"45";
+       constant SC_1 : std_logic_vector(7 downto 0) := x"16";
+       constant SC_2 : std_logic_vector(7 downto 0) := x"1e";
+       constant SC_3 : std_logic_vector(7 downto 0) := x"26";
+       constant SC_4 : std_logic_vector(7 downto 0) := x"25";
+       constant SC_5 : std_logic_vector(7 downto 0) := x"2e";
+       constant SC_6 : std_logic_vector(7 downto 0) := x"36";
+       constant SC_7 : std_logic_vector(7 downto 0) := x"3d";
+       constant SC_8 : std_logic_vector(7 downto 0) := x"3e";
+       constant SC_9 : std_logic_vector(7 downto 0) := x"46";
+
+       constant SC_KP_PLUS : std_logic_vector(7 downto 0) := x"79";
+       constant SC_KP_MINUS : std_logic_vector(7 downto 0) := x"7b";
+       constant SC_KP_MUL : std_logic_vector(7 downto 0) := x"7c";
+       constant SC_KP_DIV : std_logic_vector(7 downto 0) := x"4a"; -- inkl. 0xe0!
+
+       -- fuer deutsches layout, alle anderen zeichen sind unguenstig belegt
+       constant SC_PLUS : std_logic_vector(7 downto 0) := x"5b";
+
+       constant SC_ENTER : std_logic_vector(7 downto 0) := x"5a";
+       constant SC_BKSP : std_logic_vector(7 downto 0) := x"66";
+       constant SC_SPACE : std_logic_vector(7 downto 0) := x"29";
 end package gen_pkg;
 
+package body gen_pkg is
+       procedure icwait(signal clk_i : IN std_logic; cycles: Natural) is
+       begin
+               for i in 1 to cycles loop
+                       wait until clk_i= '0' and clk_i'event;
+               end loop;
+       end;
+end package body gen_pkg;