alu: refactor von drei prozessmodell auf zwei prozessmodell

[hwmod.git] / src / gen_pkg.vhd

diff --git a/src/gen_pkg.vhd b/src/gen_pkg.vhd
index 9e27eae8a8a5435133247d081f8d788325b2e7e5..d97b94350ac47ac3d0dc1492805ea44497df84cb 100644 (file)
--- a/src/gen_pkg.vhd
+++ b/src/gen_pkg.vhd
@@ -14,7 +14,7 @@ package gen_pkg is
 
        constant CBITS : integer := 32;
        subtype csigned is signed((CBITS-1) downto 0);
-       subtype divinteger is integer range -33 to 33;
+       subtype divinteger is unsigned(4 downto 0);
        -- integer ist 32bit (31bit + sign)
        subtype cinteger is integer;
 
@@ -27,7 +27,6 @@ package gen_pkg is
        subtype hstring is string(1 to 72);
        subtype hstr_int is integer range 0 to 72;
 
-       function find_msb(a : csigned) return divinteger;
        procedure icwait(signal clk_i : IN std_logic; cycles: natural);
 
        -- http://www.marjorie.de/ps2/scancode-set2.htm
@@ -42,27 +41,31 @@ package gen_pkg is
        constant SC_KP_8 : std_logic_vector(7 downto 0) := x"75";
        constant SC_KP_9 : std_logic_vector(7 downto 0) := x"7d";
 
+       constant SC_0 : std_logic_vector(7 downto 0) := x"45";
+       constant SC_1 : std_logic_vector(7 downto 0) := x"16";
+       constant SC_2 : std_logic_vector(7 downto 0) := x"1e";
+       constant SC_3 : std_logic_vector(7 downto 0) := x"26";
+       constant SC_4 : std_logic_vector(7 downto 0) := x"25";
+       constant SC_5 : std_logic_vector(7 downto 0) := x"2e";
+       constant SC_6 : std_logic_vector(7 downto 0) := x"36";
+       constant SC_7 : std_logic_vector(7 downto 0) := x"3d";
+       constant SC_8 : std_logic_vector(7 downto 0) := x"3e";
+       constant SC_9 : std_logic_vector(7 downto 0) := x"46";
+
        constant SC_KP_PLUS : std_logic_vector(7 downto 0) := x"79";
        constant SC_KP_MINUS : std_logic_vector(7 downto 0) := x"7b";
        constant SC_KP_MUL : std_logic_vector(7 downto 0) := x"7c";
        constant SC_KP_DIV : std_logic_vector(7 downto 0) := x"4a"; -- inkl. 0xe0!
 
+       -- fuer deutsches layout, alle anderen zeichen sind unguenstig belegt
+       constant SC_PLUS : std_logic_vector(7 downto 0) := x"5b";
+
        constant SC_ENTER : std_logic_vector(7 downto 0) := x"5a";
        constant SC_BKSP : std_logic_vector(7 downto 0) := x"66";
        constant SC_SPACE : std_logic_vector(7 downto 0) := x"29";
 end package gen_pkg;
 
 package body gen_pkg is
-       function find_msb(a : csigned) return divinteger is
-               variable r : divinteger := 0;
-       begin
-               for i in (CBITS-1) downto 0 loop
-                       exit when a(i) = '1';
-                       r := r+1;
-               end loop;
-               return (CBITS - r);
-       end function find_msb;
-
        procedure icwait(signal clk_i : IN std_logic; cycles: Natural) is
        begin
                for i in 1 to cycles loop
@@ -70,4 +73,3 @@ package body gen_pkg is
                end loop;
        end;
 end package body gen_pkg;
-