-- integer ist 32bit (31bit + sign)
subtype cinteger is integer;
- -- 50 zeilen * 71 zeichen * 2 (berechnung + ergebnis) = 7100 bytes
- constant H_RAM_SIZE : integer := 7100;
- constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE);
+
+ constant HSPALTE_MAX : integer := 71;
subtype hspalte is std_logic_vector(6 downto 0);
+
+ constant HZEILE_MAX : integer := 100;
subtype hzeile is std_logic_vector(6 downto 0);
+
+ -- 50 zeilen * 71 zeichen * 2 (berechnung + ergebnis) = 7100 bytes
+ constant H_RAM_SIZE : integer := HZEILE_MAX * HSPALTE_MAX;
+ constant H_RAM_WIDTH : integer := log2c(H_RAM_SIZE);
+
subtype hbyte is std_logic_vector(7 downto 0);
- subtype hstring is string(1 to 72);
- subtype hstr_int is integer range 0 to 72;
+ subtype hstring is string(1 to HSPALTE_MAX+1);
+ subtype hstr_int is integer range 0 to HSPALTE_MAX+1;
procedure icwait(signal clk_i : IN std_logic; cycles: natural);
+ function ascii2sc (x : hbyte) return hbyte;
+ function valid_char (x : hbyte) return boolean;
+ function zeile2char(i : std_logic_vector; stelle : natural) return hbyte;
+
-- http://www.marjorie.de/ps2/scancode-set2.htm
- constant SC_KP_0 : std_logic_vector(7 downto 0) := x"70";
- constant SC_KP_1 : std_logic_vector(7 downto 0) := x"69";
- constant SC_KP_2 : std_logic_vector(7 downto 0) := x"72";
- constant SC_KP_3 : std_logic_vector(7 downto 0) := x"7a";
- constant SC_KP_4 : std_logic_vector(7 downto 0) := x"6b";
- constant SC_KP_5 : std_logic_vector(7 downto 0) := x"73";
- constant SC_KP_6 : std_logic_vector(7 downto 0) := x"74";
- constant SC_KP_7 : std_logic_vector(7 downto 0) := x"6c";
- constant SC_KP_8 : std_logic_vector(7 downto 0) := x"75";
- constant SC_KP_9 : std_logic_vector(7 downto 0) := x"7d";
-
- constant SC_0 : std_logic_vector(7 downto 0) := x"45";
- constant SC_1 : std_logic_vector(7 downto 0) := x"16";
- constant SC_2 : std_logic_vector(7 downto 0) := x"1e";
- constant SC_3 : std_logic_vector(7 downto 0) := x"26";
- constant SC_4 : std_logic_vector(7 downto 0) := x"25";
- constant SC_5 : std_logic_vector(7 downto 0) := x"2e";
- constant SC_6 : std_logic_vector(7 downto 0) := x"36";
- constant SC_7 : std_logic_vector(7 downto 0) := x"3d";
- constant SC_8 : std_logic_vector(7 downto 0) := x"3e";
- constant SC_9 : std_logic_vector(7 downto 0) := x"46";
-
- constant SC_KP_PLUS : std_logic_vector(7 downto 0) := x"79";
- constant SC_KP_MINUS : std_logic_vector(7 downto 0) := x"7b";
- constant SC_KP_MUL : std_logic_vector(7 downto 0) := x"7c";
- constant SC_KP_DIV : std_logic_vector(7 downto 0) := x"4a"; -- inkl. 0xe0!
+ constant SC_KP_0 : hbyte := x"70";
+ constant SC_KP_1 : hbyte := x"69";
+ constant SC_KP_2 : hbyte := x"72";
+ constant SC_KP_3 : hbyte := x"7a";
+ constant SC_KP_4 : hbyte := x"6b";
+ constant SC_KP_5 : hbyte := x"73";
+ constant SC_KP_6 : hbyte := x"74";
+ constant SC_KP_7 : hbyte := x"6c";
+ constant SC_KP_8 : hbyte := x"75";
+ constant SC_KP_9 : hbyte := x"7d";
+
+ constant SC_0 : hbyte := x"45";
+ constant SC_1 : hbyte := x"16";
+ constant SC_2 : hbyte := x"1e";
+ constant SC_3 : hbyte := x"26";
+ constant SC_4 : hbyte := x"25";
+ constant SC_5 : hbyte := x"2e";
+ constant SC_6 : hbyte := x"36";
+ constant SC_7 : hbyte := x"3d";
+ constant SC_8 : hbyte := x"3e";
+ constant SC_9 : hbyte := x"46";
+
+ constant SC_KP_PLUS : hbyte := x"79";
+ constant SC_KP_MINUS : hbyte := x"7b";
+ constant SC_KP_MUL : hbyte := x"7c";
+ constant SC_KP_DIV : hbyte := x"4a"; -- inkl. 0xe0!
-- fuer deutsches layout, alle anderen zeichen sind unguenstig belegt
- constant SC_PLUS : std_logic_vector(7 downto 0) := x"5b";
+ constant SC_PLUS : hbyte := x"5b";
+
+ constant SC_ENTER : hbyte := x"5a";
+ constant SC_BKSP : hbyte := x"66";
+ constant SC_SPACE : hbyte := x"29";
+
+ -- components...
+ component alu is
+ port (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ opcode : in alu_ops;
+ op1 : in csigned;
+ op2 : in csigned;
+ op3 : out csigned;
+ opM : out csigned;
+ do_calc : in std_logic;
+ calc_done : out std_logic;
+ calc_error : out std_logic
+ );
+ end component alu;
+
+ component parser is
+ port (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ -- History
+ p_rget : out std_logic;
+ p_rdone : in std_logic;
+ p_read : in hbyte;
+ p_wtake : out std_logic;
+ p_wdone : in std_logic;
+ p_write : out hbyte;
+ p_finished : out std_logic;
+ -- Scanner
+ do_it : in std_logic;
+ finished : out std_logic
+ );
+ end component parser;
- constant SC_ENTER : std_logic_vector(7 downto 0) := x"5a";
- constant SC_BKSP : std_logic_vector(7 downto 0) := x"66";
- constant SC_SPACE : std_logic_vector(7 downto 0) := x"29";
+ component scanner is
+ port (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ -- PS/2
+ new_data : in std_logic;
+ data : in std_logic_vector(7 downto 0);
+ -- History
+ s_char : out hbyte;
+ s_take : out std_logic;
+ s_done : in std_logic;
+ s_backspace : out std_logic;
+ -- Parser
+ do_it : out std_logic;
+ finished : in std_logic
+ );
+ end component scanner;
+
+ component history is
+ port (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ -- PC-komm
+ pc_get : in std_logic;
+ pc_spalte : in hspalte;
+ pc_zeile : in hzeile;
+ pc_char : out hbyte;
+ pc_done : out std_logic;
+ -- Scanner
+ s_char : in hbyte;
+ s_take : in std_logic;
+ s_done : out std_logic;
+ s_backspace : in std_logic;
+ -- Display
+ d_new_eingabe : out std_logic;
+ d_new_result : out std_logic;
+ d_new_bs : out std_logic;
+ d_zeile : in hzeile;
+ d_spalte : in hspalte;
+ d_get : in std_logic;
+ d_done : out std_logic;
+ d_char : out hbyte;
+ -- Parser
+ p_rget : in std_logic;
+ p_rdone : out std_logic;
+ p_read : out hbyte;
+ p_wtake : in std_logic;
+ p_wdone : out std_logic;
+ p_write : in hbyte;
+ p_finished : in std_logic
+ );
+ end component history;
+
+ component display is
+ port (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ -- History
+ d_new_eingabe : in std_logic;
+ d_new_result : in std_logic;
+ d_new_bs : in std_logic;
+ d_zeile : out hzeile;
+ d_spalte : out hspalte;
+ d_get : out std_logic;
+ d_done : in std_logic;
+ d_char : in hbyte;
+ -- VGA
+ command : out std_logic_vector(7 downto 0);
+ command_data : out std_logic_vector(31 downto 0);
+ free : in std_logic
+ );
+ end component display;
+
+ component pc_communication is
+ port (
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ --button
+ btn_a : in std_logic;
+ --uart_tx
+ tx_data : out std_logic_vector(7 downto 0);
+ tx_new : out std_logic;
+ tx_done : in std_logic;
+ --uart_rx
+ rx_data : in std_logic_vector(7 downto 0);
+ rx_new : in std_logic;
+ -- History
+ pc_zeile : out hzeile;
+ pc_spalte : out hspalte;
+ pc_get : out std_logic;
+ pc_done : in std_logic;
+ pc_char : in hbyte
+ );
+ end component pc_communication;
+
+ component uart_rx is
+ generic (
+ CLK_FREQ : integer := 33000000;
+ BAUDRATE : integer := 115200
+ );
+ port(
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ rxd : in std_logic;
+ rx_data : out std_logic_vector(7 downto 0);
+ rx_new : out std_logic
+ );
+ end component uart_rx;
+
+ component uart_tx is
+ generic (
+ CLK_FREQ : integer := 33000000;
+ BAUDRATE : integer := 115200
+ );
+ port(
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ txd : out std_logic;
+ tx_data : in std_logic_vector(7 downto 0);
+ tx_new : in std_logic;
+ tx_done : out std_logic
+ );
+ end component uart_tx;
+
+ component vpll IS
+ port (
+ inclk0 : in std_logic := '0';
+ c0 : out std_logic
+ );
+ end component vpll;
+
+ component clk_vga_s3e is
+ port (
+ clk50 : in std_logic;
+ clk25 : out std_logic
+ );
+ end component clk_vga_s3e;
+
+ component sp_ram is
+ generic (
+ ADDR_WIDTH : integer range 1 to integer'high
+ );
+ port (
+ sys_clk : in std_logic;
+ address : in std_logic_vector(ADDR_WIDTH - 1 downto 0);
+ data_out : out hbyte;
+ wr : in std_logic;
+ data_in : in hbyte
+ );
+ end component sp_ram;
end package gen_pkg;
package body gen_pkg is
wait until clk_i= '0' and clk_i'event;
end loop;
end;
+
+ function ascii2sc (x : hbyte) return hbyte is
+ variable y : hbyte;
+ begin
+ case x is
+ when x"30" => y := SC_KP_0;
+ when x"31" => y := SC_KP_1;
+ when x"32" => y := SC_KP_2;
+ when x"33" => y := SC_KP_3;
+ when x"34" => y := SC_KP_4;
+ when x"35" => y := SC_KP_5;
+ when x"36" => y := SC_KP_6;
+ when x"37" => y := SC_KP_7;
+ when x"38" => y := SC_KP_8;
+ when x"39" => y := SC_KP_9;
+ when x"2b" => y := SC_KP_PLUS;
+ when x"2d" => y := SC_KP_MINUS;
+ when x"2a" => y := SC_KP_MUL;
+ when x"2f" => y := SC_KP_DIV;
+ when x"20" => y := SC_SPACE;
+ when x"1c" => y := SC_ENTER;
+ when x"0e" => y := SC_BKSP;
+ when others => y := x"41";
+ end case;
+ return y;
+ end function;
+
+ function valid_char (x : hbyte) return boolean is
+ variable y : boolean;
+ begin
+ case x is
+ when SC_KP_0 | SC_KP_1 | SC_KP_2 | SC_KP_3 |
+ SC_KP_4 | SC_KP_5 | SC_KP_6 | SC_KP_7 |
+ SC_KP_8 | SC_KP_9 | SC_KP_PLUS |
+ SC_KP_MINUS | SC_KP_MUL |
+ SC_KP_DIV | SC_SPACE |
+ SC_BKSP | SC_ENTER =>
+ y := true;
+ when others => y := false;
+ end case;
+ return y;
+ end function;
+
+ function zeile2char(i : std_logic_vector; stelle : natural) return hbyte is
+ subtype zeilnum is string(1 to 2);
+ type zeilnum_arr is array (natural range 0 to 49) of zeilnum;
+ constant zn : zeilnum_arr := (
+ 0 => "00", 1 => "01", 2 => "02", 3 => "03", 4 => "04",
+ 5 => "05", 6 => "06", 7 => "07", 8 => "08", 9 => "09",
+ 10 => "10", 11 => "11", 12 => "12", 13 => "13", 14 => "14",
+ 15 => "15", 16 => "16", 17 => "17", 18 => "18", 19 => "19",
+ 20 => "20", 21 => "21", 22 => "22", 23 => "23", 24 => "24",
+ 25 => "25", 26 => "26", 27 => "27", 28 => "28", 29 => "29",
+ 30 => "30", 31 => "31", 32 => "32", 33 => "33", 34 => "34",
+ 35 => "35", 36 => "36", 37 => "37", 38 => "38", 39 => "39",
+ 40 => "40", 41 => "41", 42 => "42", 43 => "43", 44 => "44",
+ 45 => "45", 46 => "46", 47 => "47", 48 => "48", 49 => "49",
+ others => "xy");
+ variable t : signed(hzeile'length downto 0);
+ begin
+ t := signed('0' & i);
+ t := t / 2;
+ return hbyte(to_unsigned(character'pos(zn(to_integer(t))(stelle)),8));
+ end;
end package body gen_pkg;
projects / hwmod.git / blobdiff