signal rx_data : std_logic_vector (7 downto 0);
signal tx_new, tx_done : std_logic;
signal tx_data : std_logic_vector (7 downto 0);
- signal txd_out : std_logic;
begin
-- vga/ipcore
textmode_vga_inst : entity work.textmode_vga(struct)
p_wtake => p_wtake,
p_wdone => p_wdone,
p_write => p_write,
- p_finished => p_finished
+ p_finished => p_finished,
+ -- pc communication
+ pc_get => '0',
+ pc_spalte => (others => '0'),
+ pc_zeile => (others => '0'),
+ pc_char => open,
+ pc_done => open
+
);
-- parser
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n,
- txd => txd_out,
+ txd => txd,
tx_data => tx_data,
tx_new => tx_new,
tx_done => tx_done