added pc-communication to history

[hwmod.git] / src / calc.vhd

diff --git a/src/calc.vhd b/src/calc.vhd
index 41250e1432867e1a56e6ed73b774eb0ab85a7311..d398bd31ffe170a3577f7c97312bbc7933c10f87 100644 (file)
--- a/src/calc.vhd
+++ b/src/calc.vhd
@@ -6,6 +6,8 @@ use work.textmode_vga_component_pkg.all;
 use work.textmode_vga_pkg.all;
 use work.textmode_vga_platform_dependent_pkg.all;
 use work.ps2_keyboard_controller_pkg.all;
+use work.debounce_pkg.all;
+use work.sync_pkg.all;
 
 entity calc is
        port (
@@ -14,7 +16,8 @@ entity calc is
                -- btnA
                -- TODO: pins
                -- rs232
-               -- TODO: pins
+               rxd : in std_logic;
+               txd : out std_logic;
                -- vga
                vsync_n : out std_logic;
                hsync_n : out std_logic;
@@ -55,6 +58,13 @@ architecture top of calc is
        signal p_finished : std_logic;
        -- parser/scanner
        signal do_it, finished : std_logic;
+       -- debouncing
+       signal sys_res_n_sync : std_logic;
+       -- rs232
+       signal rx_new, rxd_sync : std_logic;
+       signal rx_data : std_logic_vector (7 downto 0);
+       signal tx_new, tx_done : std_logic;
+       signal tx_data : std_logic_vector (7 downto 0);
 begin
        -- vga/ipcore
        textmode_vga_inst : entity work.textmode_vga(struct)
@@ -65,12 +75,12 @@ begin
        )
        port map (
                sys_clk => sys_clk,
-               sys_res_n => sys_res_n,
+               sys_res_n => sys_res_n_sync,
                command => command,
                command_data => command_data,
                free => free,
                vga_clk => vga_clk,
-               vga_res_n => sys_res_n,
+               vga_res_n => sys_res_n_sync,
                vsync_n => vsync_n,
                hsync_n => hsync_n,
                r => r,
@@ -89,7 +99,7 @@ begin
        display_inst : entity work.display(beh)
        port map (
                sys_clk => sys_clk,
-               sys_res_n => sys_res_n,
+               sys_res_n => sys_res_n_sync,
                -- history
                d_new_eingabe => d_new_eingabe,
                d_new_result => d_new_result,
@@ -109,7 +119,7 @@ begin
        history_inst : entity work.history(beh)
        port map (
                sys_clk => sys_clk,
-               sys_res_n => sys_res_n,
+               sys_res_n => sys_res_n_sync,
                -- scanner
                s_char => s_char,
                s_take => s_take,
@@ -131,14 +141,21 @@ begin
                p_wtake => p_wtake,
                p_wdone => p_wdone,
                p_write => p_write,
-               p_finished => p_finished
+               p_finished => p_finished,
+               -- pc communication
+               pc_get =>  '0',
+               pc_spalte => (others => '0'),
+               pc_zeile => (others => '0'),
+               pc_char => open,
+               pc_done => open
+
        );
 
        -- parser
        parser_inst : entity work.parser(beh)
        port map (
                sys_clk => sys_clk,
-               sys_res_n => sys_res_n,
+               sys_res_n => sys_res_n_sync,
                -- history
                p_rget => p_rget,
                p_rdone => p_rdone,
@@ -156,7 +173,7 @@ begin
        scanner_inst : entity work.scanner(beh)
        port map (
                sys_clk => sys_clk,
-               sys_res_n => sys_res_n,
+               sys_res_n => sys_res_n_sync,
                -- ps/2
                new_data => new_data,
                data => data,
@@ -178,12 +195,69 @@ begin
        )
        port map (
                sys_clk => sys_clk,
-               sys_res_n => sys_res_n,
+               sys_res_n => sys_res_n_sync,
                -- scanner
                new_data => new_data,
                data => data,
                ps2_clk => ps2_clk,
                ps2_data => ps2_data
        );
+
+       -- debouncer fuer sys_res_n
+       sys_res_n_debounce_inst : debounce
+       generic map (
+               CLK_FREQ => 33330000,
+               TIMEOUT => 1 ms,
+               RESET_VALUE => '1',
+               SYNC_STAGES => 2
+       )
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => '1',
+               data_in => sys_res_n,
+               data_out => sys_res_n_sync
+       );
+
+       -- synchronizer fuer rxd
+       sync_rxd_inst : entity work.sync(beh)
+       generic map (
+               SYNC_STAGES => 2,
+               RESET_VALUE => '1'
+       )
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n_sync,
+               data_in => rxd,
+               data_out => rxd_sync
+       );
+
+       -- rs232-rx
+       rs232rx_inst : entity work.uart_rx(beh)
+       generic map (
+               CLK_FREQ => 33330000,
+               BAUDRATE => 115200
+       )
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n_sync,
+               rxd => rxd_sync,
+               rx_data => rx_data,
+               rx_new => rx_new
+       );
+
+       -- rs232-tx
+       rs232tx_inst : entity work.uart_tx(beh)
+       generic map (
+               CLK_FREQ => 33330000,
+               BAUDRATE => 115200
+       )
+       port map (
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n,
+               txd => txd,
+               tx_data => tx_data,
+               tx_new => tx_new,
+               tx_done => tx_done
+       );
 end architecture top;