--- TODO: dient im moment nur als "fake top entity"
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;
+use work.textmode_vga_component_pkg.all;
+use work.textmode_vga_pkg.all;
+use work.textmode_vga_platform_dependent_pkg.all;
+use work.ps2_keyboard_controller_pkg.all;
+use work.debounce_pkg.all;
+use work.sync_pkg.all;
entity calc is
- port
- (
+ port (
sys_clk : in std_logic;
- sys_res_n : in std_logic
+ sys_res_n : in std_logic;
+ -- btnA
+ -- TODO: pins
+ -- rs232
+ -- TODO: pins
+ -- vga
+ vsync_n : out std_logic;
+ hsync_n : out std_logic;
+ r : out std_logic_vector(RED_BITS - 1 downto 0);
+ g : out std_logic_vector(GREEN_BITS - 1 downto 0);
+ b : out std_logic_vector(BLUE_BITS - 1 downto 0);
+ -- ps/2
+ ps2_clk : inout std_logic;
+ ps2_data : inout std_logic
);
end entity calc;
architecture top of calc is
- component alu is
- port
- (
- sys_clk : in std_logic;
- sys_res_n : in std_logic;
- opcode : in alu_ops;
- op1 : in csigned;
- op2 : in csigned;
- op3 : out csigned;
- do_calc : in std_logic;
- calc_done : out std_logic
- );
- end component alu;
-
- signal do_calc, calc_done : std_logic;
- signal opcode : alu_ops;
- signal op1, op2, op3 : csigned;
+ -- ps/2
+ signal new_data : std_logic;
+ signal data : std_logic_vector(7 downto 0);
+ -- vga
+ signal vga_clk, free : std_logic;
+ -- vga/display
+ signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
+ signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
+ -- history/display
+ signal d_new_eingabe, d_new_result, d_new_bs : std_logic;
+ signal d_zeile : hzeile;
+ signal d_spalte : hspalte;
+ signal d_get, d_done : std_logic;
+ signal d_char : hbyte;
+ -- history/scanner
+ signal s_char : hbyte;
+ signal s_take, s_done, s_backspace : std_logic;
+ -- history/parser
+ signal p_rget : std_logic;
+ signal p_rdone : std_logic;
+ signal p_read : hbyte;
+ signal p_wtake : std_logic;
+ signal p_wdone : std_logic;
+ signal p_write : hbyte;
+ signal p_finished : std_logic;
+ -- parser/scanner
+ signal do_it, finished : std_logic;
+ -- debouncing
+ signal sys_res_n_sync : std_logic;
begin
- aluc : alu
- port map
- (
+ -- vga/ipcore
+ textmode_vga_inst : entity work.textmode_vga(struct)
+ generic map (
+ VGA_CLK_FREQ => 25000000,
+ BLINK_INTERVAL_MS => 500,
+ SYNC_STAGES => 2
+ )
+ port map (
sys_clk => sys_clk,
- sys_res_n => sys_res_n,
- do_calc => do_calc,
- calc_done => calc_done,
- op1 => op1,
- op2 => op2,
- op3 => op3,
- opcode => opcode
- );
-
- process (sys_clk, sys_res_n)
- begin
- if sys_res_n = '0' then
- op1 <= (others => '0');
- opcode <= NOP;
- op2 <= (others => '0');
- do_calc <= '0';
- elsif rising_edge(sys_clk) then
- op1 <= op3;
- opcode <= DIV;
- op2 <= to_signed(2,CBITS);
-
- do_calc <= calc_done;
- end if;
- end process;
+ sys_res_n => sys_res_n_sync,
+ command => command,
+ command_data => command_data,
+ free => free,
+ vga_clk => vga_clk,
+ vga_res_n => sys_res_n_sync,
+ vsync_n => vsync_n,
+ hsync_n => hsync_n,
+ r => r,
+ g => g,
+ b => b
+ );
+
+ -- pll fuer vga
+ vpll_inst : entity work.vpll(syn)
+ port map (
+ inclk0 => sys_clk,
+ c0 => vga_clk
+ );
+
+ -- display
+ display_inst : entity work.display(beh)
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n_sync,
+ -- history
+ d_new_eingabe => d_new_eingabe,
+ d_new_result => d_new_result,
+ d_new_bs => d_new_bs,
+ d_zeile => d_zeile,
+ d_spalte => d_spalte,
+ d_get => d_get,
+ d_done => d_done,
+ d_char => d_char,
+ -- vga
+ command => command,
+ command_data => command_data,
+ free => free
+ );
+
+ -- history
+ history_inst : entity work.history(beh)
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n_sync,
+ -- scanner
+ s_char => s_char,
+ s_take => s_take,
+ s_done => s_done,
+ s_backspace => s_backspace,
+ -- display
+ d_new_eingabe => d_new_eingabe,
+ d_new_result => d_new_result,
+ d_new_bs => d_new_bs,
+ d_zeile => d_zeile,
+ d_spalte => d_spalte,
+ d_get => d_get,
+ d_done => d_done,
+ d_char => d_char,
+ -- parser
+ p_rget => p_rget,
+ p_rdone => p_rdone,
+ p_read => p_read,
+ p_wtake => p_wtake,
+ p_wdone => p_wdone,
+ p_write => p_write,
+ p_finished => p_finished
+ );
+
+ -- parser
+ parser_inst : entity work.parser(beh)
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n_sync,
+ -- history
+ p_rget => p_rget,
+ p_rdone => p_rdone,
+ p_read => p_read,
+ p_wtake => p_wtake,
+ p_wdone => p_wdone,
+ p_write => p_write,
+ p_finished => p_finished,
+ -- scanner
+ do_it => do_it,
+ finished => finished
+ );
+
+ -- scanner
+ scanner_inst : entity work.scanner(beh)
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n_sync,
+ -- ps/2
+ new_data => new_data,
+ data => data,
+ -- history
+ s_char => s_char,
+ s_take => s_take,
+ s_done => s_done,
+ s_backspace => s_backspace,
+ -- parser
+ do_it => do_it,
+ finished => finished
+ );
+
+ -- ps/2
+ ps2_inst : entity work.ps2_keyboard_controller(beh)
+ generic map (
+ CLK_FREQ => 33330000,
+ SYNC_STAGES => 2
+ )
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n_sync,
+ -- scanner
+ new_data => new_data,
+ data => data,
+ ps2_clk => ps2_clk,
+ ps2_data => ps2_data
+ );
+
+ -- debouncer fuer sys_res_n
+ sys_res_n_debounce_inst : debounce
+ generic map (
+ CLK_FREQ => 33330000,
+ TIMEOUT => 1 ms,
+ RESET_VALUE => '1',
+ SYNC_STAGES => 2
+ )
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => '1',
+ data_in => sys_res_n,
+ data_out => sys_res_n_sync
+ );
end architecture top;
projects / hwmod.git / blobdiff