-- btnA
-- TODO: pins
-- rs232
- -- TODO: pins
+ rxd : in std_logic;
+ txd : out std_logic;
-- vga
vsync_n : out std_logic;
hsync_n : out std_logic;
signal do_it, finished : std_logic;
-- debouncing
signal sys_res_n_sync : std_logic;
+ -- rs232
+ signal rx_new, rxd_sync : std_logic;
+ signal rx_data : std_logic_vector (7 downto 0);
+ signal tx_new, tx_done : std_logic;
+ signal tx_data : std_logic_vector (7 downto 0);
+ signal txd_out : std_logic;
begin
-- vga/ipcore
textmode_vga_inst : entity work.textmode_vga(struct)
data_in => sys_res_n,
data_out => sys_res_n_sync
);
+
+ -- synchronizer fuer rxd
+ sync_rxd_inst : entity work.sync(beh)
+ generic map (
+ SYNC_STAGES => 2,
+ RESET_VALUE => '1'
+ )
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n_sync,
+ data_in => rxd,
+ data_out => rxd_sync
+ );
+
+ -- rs232-rx
+ rs232rx_inst : entity work.uart_rx(beh)
+ generic map (
+ CLK_FREQ => 33330000,
+ BAUDRATE => 115200
+ )
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n_sync,
+ rxd => rxd_sync,
+ rx_data => rx_data,
+ rx_new => rx_new
+ );
+
+ -- rs232-tx
+ rs232tx_inst : entity work.uart_tx(beh)
+ generic map (
+ CLK_FREQ => 33330000,
+ BAUDRATE => 115200
+ )
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ txd => txd_out,
+ tx_data => tx_data,
+ tx_new => tx_new,
+ tx_done => tx_done
+ );
end architecture top;