sys_clk : in std_logic;
sys_res_n : in std_logic;
-- btnA
- -- TODO: pins
+ btn_a : in std_logic;
-- rs232
- -- TODO: pins
+ rxd : in std_logic;
+ txd : out std_logic;
-- vga
vsync_n : out std_logic;
hsync_n : out std_logic;
signal p_wdone : std_logic;
signal p_write : hbyte;
signal p_finished : std_logic;
+ --history/pc_com
+ signal pc_get : std_logic;
+ signal pc_spalte : hspalte;
+ signal pc_zeile : hzeile;
+ signal pc_char : hbyte;
+ signal pc_done : std_logic;
-- parser/scanner
signal do_it, finished : std_logic;
-- debouncing
signal sys_res_n_sync : std_logic;
+ -- rs232
+ signal rx_new, rxd_sync : std_logic;
+ signal rx_data : std_logic_vector (7 downto 0);
+ signal tx_new, tx_done : std_logic;
+ signal tx_data : std_logic_vector (7 downto 0);
+
+ signal btn_a_sync : std_logic;
+
begin
-- vga/ipcore
textmode_vga_inst : entity work.textmode_vga(struct)
p_wtake => p_wtake,
p_wdone => p_wdone,
p_write => p_write,
- p_finished => p_finished
+ p_finished => p_finished,
+ -- pc communication
+ pc_get => pc_get,
+ pc_spalte => pc_spalte,
+ pc_zeile => pc_zeile,
+ pc_char => pc_char,
+ pc_done => pc_done
+
);
-- parser
data_in => sys_res_n,
data_out => sys_res_n_sync
);
+
+ -- synchronizer fuer rxd
+ sync_rxd_inst : entity work.sync(beh)
+ generic map (
+ SYNC_STAGES => 2,
+ RESET_VALUE => '1'
+ )
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n_sync,
+ data_in => rxd,
+ data_out => rxd_sync
+ );
+
+ -- debouncer fuer btn_a
+ btn_a_debounce_inst : debounce
+ generic map (
+ CLK_FREQ => 33330000,
+ TIMEOUT => 1 ms,
+ RESET_VALUE => '1',
+ SYNC_STAGES => 2
+ )
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => '1',
+ data_in => btn_a,
+ data_out => btn_a_sync
+ );
+
+ -- rs232-rx
+ rs232rx_inst : entity work.uart_rx(beh)
+ generic map (
+ CLK_FREQ => 33330000,
+ BAUDRATE => 115200
+ )
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n_sync,
+ rxd => rxd_sync,
+ rx_data => rx_data,
+ rx_new => rx_new
+ );
+
+ -- rs232-tx
+ rs232tx_inst : entity work.uart_tx(beh)
+ generic map (
+ CLK_FREQ => 33330000,
+ BAUDRATE => 115200
+ )
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ txd => txd,
+ tx_data => tx_data,
+ tx_new => tx_new,
+ tx_done => tx_done
+ );
+
+ pc_com_inst : entity work.pc_communication(beh)
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ --button
+ btn_a => btn_a_sync,
+ --uart_tx
+ tx_data => tx_data,
+ tx_new => tx_new,
+ tx_done => tx_done,
+ --uart_rx
+ rx_data => rx_data,
+ rx_new => rx_new,
+ -- History
+ d_zeile => pc_zeile,
+ d_spalte => pc_spalte,
+ d_get => pc_get,
+ d_done => pc_done,
+ d_char => pc_char
+ );
+
end architecture top;