uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / beh_uart_tx_tb.vhd

diff --git a/src/beh_uart_tx_tb.vhd b/src/beh_uart_tx_tb.vhd
index a02ac726b72fa3ecdc42be0aa2a1a53876552faf..db4453c1828ff6a8ac1c43670fbab3b00a960843 100644 (file)
--- a/src/beh_uart_tx_tb.vhd
+++ b/src/beh_uart_tx_tb.vhd
@@ -7,48 +7,92 @@ entity beh_uart_tx_tb is
 end entity beh_uart_tx_tb;
 
 architecture sim of beh_uart_tx_tb is
+       constant CLK_FREQ : integer := 33000000;
+       constant BAUDRATE : integer := 115200;
+       constant BAUD : integer := CLK_FREQ/BAUDRATE;
 
-       constant clk_period  : time := 10ns;
-       signal clock : std_logic;
-       signal reset : std_logic;
-       signal done : std_logic;
-       signal newsig : std_logic;
+       signal sys_clk, sys_res_n, txd, tx_new, tx_done : std_logic;
+       signal tx_data : std_logic_vector (7 downto 0);
+       signal stop : boolean := false;
 begin
-       inst : entity work.uart_tx(beh)
+       inst : uart_tx
+       generic map (
+               CLK_FREQ => CLK_FREQ,
+               BAUDRATE => BAUDRATE
+       )
        port map (
-                sys_clk => clock,
-                sys_res => reset,
-                --=> txd,
-                --=> tx_data,
-                tx_new => newsig,
-                tx_done => done
+               sys_clk => sys_clk,
+               sys_res_n => sys_res_n,
+               txd => txd,
+               tx_data => tx_data,
+               tx_new => tx_new,
+               tx_done => tx_done
        );
 
-       stimuli : process
+       process
        begin
-               newsig <= '0';
-               wait for 10ns;
-               --send 'Hallo Welt'
-               newsig <= '1';
-               wait for 1000ns;
+               sys_clk <= '0';
+               wait for 15 ns;
+               sys_clk <= '1';
+               wait for 15 ns;
+               if stop = true then
+                       wait;
+               end if;
+       end process;
 
-               assert false report "Test finished" severity failure;
-       end process stimuli;
+       process
+               procedure exec_tc(testnr : integer;
+                       constant expectedresult : std_logic_vector(9 downto 0);
+                       constant testvector : std_logic_vector(7 downto 0)) is
+                       variable success : boolean := true;
+               begin
+                       tx_new <= '1';
+                       tx_data <= testvector;
+                       icwait(sys_clk, 1);
 
-       res_gen : process
-       begin
-               reset <= '0';
-               wait for 20ns;
-               reset <= '1';
-               wait for 1000ns;
-       end process res_gen;
+                       -- ein BAUD-cycle auf high warten
+                       icwait(sys_clk, BAUD);
+
+                       -- in der mitte abtasten
+                       icwait(sys_clk, BAUD/2);
+                       for i in 0 to 9 loop
+                               if txd /= expectedresult(9-i) then
+                                       success := false;
+                               end if;
+                               if i /= 9 then
+                                       icwait(sys_clk, BAUD);
+                               end if;
+                       end loop;
 
-       clock_gen : process
+                       wait until tx_done = '1';
+                       tx_new <= '0';
+                       wait until tx_done = '0';
+                       if success then
+                               report "testfall " & integer'image(testnr) & " war erfolgreich";
+                       else
+                               report "testfall " & integer'image(testnr) & " schlug fehl";
+                       end if;
+                       icwait(sys_clk, 3);
+               end;
        begin
-               clock <= '0';
-               wait for clk_period/2;
-               clock <= '1';
-               wait for clk_period/2;
-       end process clock_gen;
+               sys_res_n <= '0';
+               tx_new <= '0';
+               tx_data <= (others => '0');
+               icwait(sys_clk, 10);
+               sys_res_n <= '1';
+               icwait(sys_clk, 2);
+
+               -- 1. parameter: testfallnummer
+               -- 2. parameter: STARTBIT (1 bit) - immer '0' | 8 DATENBITS (reversed) | 1 STOPBIT - immer '1'
+               -- 3. parameter: byte das gesendet werden soll
+               exec_tc(1, b"0000011111", b"11110000");
+               exec_tc(2, b"0101010101", b"01010101");
+               exec_tc(3, b"0110011001", b"00110011");
+               exec_tc(4, b"0001100111", b"11001100");
+               exec_tc(5, b"0010101011", b"10101010");
+               exec_tc(6, b"0100110111", b"11011001");
 
+               stop <= true;
+               wait;
+       end process;
 end sim;