uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / beh_uart_rx_tb.vhd

diff --git a/src/beh_uart_rx_tb.vhd b/src/beh_uart_rx_tb.vhd
index 26adbda22b46f13419dc05fe61530b19af389af3..e6d2ad55c4d7986ed43ff54a6ea2bd9f4833c86b 100644 (file)
--- a/src/beh_uart_rx_tb.vhd
+++ b/src/beh_uart_rx_tb.vhd
@@ -15,7 +15,7 @@ architecture sim of beh_uart_rx_tb is
        signal rx_data : std_logic_vector (7 downto 0);
        signal stop : boolean := false;
 begin
-       inst : entity work.uart_rx(beh)
+       inst : uart_rx
        generic map (
                CLK_FREQ => CLK_FREQ,
                BAUDRATE => BAUDRATE
@@ -75,13 +75,13 @@ begin
 
                -- 1. parameter: testfallnummer
                -- 2. parameter: STARTBIT (1 bit) - immer '0' | 8 DATENBITS | 1 STOPBIT - immer '1'
-               -- 3. parameter: byte das rauskommen soll
-               exec_tc(1, b"0000011111", b"00001111");
-               exec_tc(2, b"0101010101", b"10101010");
-               exec_tc(3, b"0110011001", b"11001100");
-               exec_tc(4, b"0001100111", b"00110011");
-               exec_tc(5, b"0010101011", b"01010101");
-               exec_tc(6, b"0100110111", b"10011011");
+               -- 3. parameter: byte das rauskommen soll (umgekehrte reihenfolge)
+               exec_tc(1, b"0000011111", b"11110000");
+               exec_tc(2, b"0101010101", b"01010101");
+               exec_tc(3, b"0110011001", b"00110011");
+               exec_tc(4, b"0001100111", b"11001100");
+               exec_tc(5, b"0010101011", b"10101010");
+               exec_tc(6, b"0100110111", b"11011001");
 
                stop <= true;
                wait;