pc and uart compile

[hwmod.git] / src / beh_pc_communication_tb.vhd

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index c8620959a8d2ddf7903a3aee32b48ed30c66abd0..ebb52b7acb816b2d808132fef5456fa67a3f6979 100644 (file)
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -6,10 +6,27 @@ use work.textmode_vga_component_pkg.all;
 use work.textmode_vga_pkg.all;
 use work.textmode_vga_platform_dependent_pkg.all;
 
+-- this is for test file io
+use std.textio.all;
+
 entity beh_pc_communication_tb is
 end entity beh_pc_communication_tb;
 
 architecture sim of beh_pc_communication_tb is
+               type byte_file_type is file of hbyte;
+               signal sys_clk : std_logic;
+               signal sys_res_n : std_logic;
+               signal btn_a : std_logic;
+               signal tx_new : std_logic;
+               signal tx_done : std_logic;
+               signal rx_new : std_logic;
+               signal d_get : std_logic;
+               signal d_done : std_logic;
+               signal rx_data, tx_data : std_logic_vector(7 downto 0);
+
+               signal d_zeile : hzeile;
+               signal d_spalte : hspalte;
+               signal d_char : hbyte;
 begin
        -- display
        inst : entity work.pc_communication(beh)
@@ -17,24 +34,24 @@ begin
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
 
-               --button=> ,
+               --button
                btn_a => btn_a,
 
-               --uart_tx=> ,
+               --uart_tx
                tx_data => tx_data,
                tx_new => tx_new,
                tx_done => tx_done,
 
-               --uart_rx=> ,
+               --uart_rx
                rx_data => rx_data,
                rx_new => rx_new,
 
-               -- History=> ,
+               -- History
                d_zeile => d_zeile,
                d_spalte => d_spalte,
                d_get => d_get,
                d_done => d_done,
-               d_char => d_char--,
+               d_char => d_char
        );
 
        clk : process
@@ -43,30 +60,34 @@ begin
                wait for 15 ns;
                sys_clk <= '1';
                wait for 15 ns;
-               if stop = true then
-                       wait;
-               end if;
        end process clk;
 
-       stub_history process (d_get)
-               file f : text open read_mode is "../../src/pc_communication.test";
+       stub_history : process
+               file f : byte_file_type open read_mode is "../../src/pc_communication.test";
+               variable rb : hbyte;
        begin
-               if rising_edge(d_get) then
-                       read(f, d_char);
-                       wait 30 ns;
-                       done <= d_done;
-               end if;
+               wait until rising_edge(d_get);
+               assert not endfile(f) report "test beendet" severity failure;
+               read(f, rb);
+               wait for 30 ns;
+               d_char <= rb;
+               d_done <= '1';
+               wait for 15 ns;
+               d_done <= '0';
        end process stub_history;
 
-       process
+       reset_and_button : process
        begin
                -- init & reset
                -- we only simulate pressing of button a by now!
-               sys_res_n <= 0;
+               sys_res_n <= '0';
                wait for 100 ns;
-               sys_res_n <= 1;
+               sys_res_n <= '1';
 
-               btn_a <= 1;
+               btn_a <= '1';
+               wait for 15ns;
+               btn_a <= '0';
                wait;
-       end process;
+       end process reset_and_button;
+
 end architecture sim;