signal tx_new : std_logic;
signal tx_done : std_logic;
signal rx_new : std_logic;
- signal d_get : std_logic;
- signal d_done : std_logic;
+ signal pc_get : std_logic;
+ signal pc_done : std_logic;
+ signal pc_busy : std_logic;
signal rx_data, tx_data : std_logic_vector(7 downto 0);
- signal d_zeile : hzeile;
- signal d_spalte : hspalte;
- signal d_char : hbyte;
+ signal pc_zeile : hzeile;
+ signal pc_spalte : hspalte;
+ signal pc_char : hbyte;
begin
- -- display
+ -- pc_communication
inst : entity work.pc_communication(beh)
port map (
sys_clk => sys_clk,
rx_new => rx_new,
-- History
- d_zeile => d_zeile,
- d_spalte => d_spalte,
- d_get => d_get,
- d_done => d_done,
- d_char => d_char
+ pc_zeile => pc_zeile,
+ pc_spalte => pc_spalte,
+ pc_get => pc_get,
+ pc_done => pc_done,
+ pc_busy => pc_busy,
+ pc_char => pc_char
);
clk : process
stub_history : process
file f : text open read_mode is "../../src/pc_communication.test";
- --variable rb : hbyte;
variable rb : character;
variable good : boolean;
variable i : integer;
variable buf : my_string;
variable l : line;
begin
- --take control of the situation.
- d_char <= (others => '0');
+ pc_char <= (others => '0');
+ pc_done <= '0';
+ pc_busy <= '0';
wait until sys_res_n = '1';
while not endfile (f) loop
readline(f, l);
+ buf := l.all;
i := 1;
while i < l'length loop
- wait until rising_edge(d_get);
- d_done <= '0';
- d_char <= (others => '0');
- wait for 90 ns;
-
- d_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
- d_done <= '1';
+ pc_done <= '0';
+ wait until rising_edge(pc_get);
+ wait for 150 ns;
+ pc_char <= (others => '0');
+ pc_busy <= '1';
+ wait for 30 ns;
+ pc_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
+ i := i + 1;
+ pc_busy <= '0';
+ pc_done <= '1';
wait for 30 ns;
-
end loop;
end loop;
stub_uart : process
begin
+ tx_done <= '0';
+ wait until sys_res_n = '1';
while true loop
tx_done <= '0';
- wait until sys_res_n = '1';
wait until rising_edge(tx_new);
wait for 300 ns;
tx_done <= '1';
-- init & reset
-- we only simulate pressing of button a by now!
sys_res_n <= '0';
- btn_a <= '0';
- tx_data <= ( others => '0');
+ btn_a <= '1';
rx_data <= ( others => '0');
- d_zeile <= ( others => '0');
- d_spalte <= ( others => '0');
rx_new <= '0';
wait for 90 ns;
sys_res_n <= '1';
wait for 30 ns;
- btn_a <= '1';
- wait for 15 ns;
btn_a <= '0';
+ wait for 30 ns;
+ btn_a <= '1';
wait;
--wait for 1000 ns;
--assert false report "test beendet" severity failure;