uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / beh_pc_communication_tb.vhd

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index ae8ed744aa2ddf41cf7241f8169ff21a12f80c15..aa921e2dfc93bab00051a9a51a84fa4b83cb4f3a 100644 (file)
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -30,7 +30,7 @@ architecture sim of beh_pc_communication_tb is
                signal pc_char : hbyte;
 begin
        -- pc_communication
-       inst : entity work.pc_communication(beh)
+       inst : pc_communication
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
@@ -65,14 +65,12 @@ begin
 
        stub_history : process
                file f : text open read_mode is "../../src/pc_communication.test";
-               --variable rb : hbyte;
                variable rb : character;
                variable good : boolean;
                variable i : integer;
                variable buf : my_string;
                variable l : line;
        begin
-               --take control of the situation.
                pc_char <= (others => '0');
                pc_done <= '0';
                wait until sys_res_n = '1';
@@ -84,14 +82,13 @@ begin
                        while i < l'length loop
                                pc_done <= '0';
                                wait until rising_edge(pc_get);
+                               wait for 150 ns;
                                pc_char <= (others => '0');
-                               wait for 300 ns;
-
+                               wait for 30 ns;
                                pc_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
                                i := i + 1;
                                pc_done <= '1';
                                wait for 30 ns;
-                               
                        end loop;
                end loop;
 
@@ -116,16 +113,16 @@ begin
                -- init & reset
                -- we only simulate pressing of button a by now!
                sys_res_n <= '0';
-               btn_a <= '0';
+               btn_a <= '1';
                rx_data <= ( others => '0');
                rx_new <= '0';
                
                wait for 90 ns;
                sys_res_n <= '1';
                wait for 30 ns;
-               btn_a <= '1';
-               wait for 30 ns;
                btn_a <= '0';
+               wait for 30 ns;
+               btn_a <= '1';
                wait;
                --wait for 1000 ns;
                --assert false report "test beendet" severity failure;