signal rx_new : std_logic;
signal pc_get : std_logic;
signal pc_done : std_logic;
- signal pc_busy : std_logic;
signal rx_data, tx_data : std_logic_vector(7 downto 0);
signal pc_zeile : hzeile;
signal pc_char : hbyte;
begin
-- pc_communication
- inst : entity work.pc_communication(beh)
+ inst : pc_communication
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n,
pc_spalte => pc_spalte,
pc_get => pc_get,
pc_done => pc_done,
- pc_busy => pc_busy,
pc_char => pc_char
);
begin
pc_char <= (others => '0');
pc_done <= '0';
- pc_busy <= '0';
wait until sys_res_n = '1';
while not endfile (f) loop
while i < l'length loop
pc_done <= '0';
wait until rising_edge(pc_get);
- wait for 90 ns;
- pc_busy <= '1';
+ wait for 150 ns;
pc_char <= (others => '0');
- wait for 300 ns;
-
+ wait for 30 ns;
pc_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
i := i + 1;
- pc_busy <= '0';
pc_done <= '1';
wait for 30 ns;
end loop;