implemented busy state

[hwmod.git] / src / beh_pc_communication_tb.vhd

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index ae8ed744aa2ddf41cf7241f8169ff21a12f80c15..9d12996ecce539546c6c302ddca3142cb56e8d5c 100644 (file)
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -23,6 +23,7 @@ architecture sim of beh_pc_communication_tb is
                signal rx_new : std_logic;
                signal pc_get : std_logic;
                signal pc_done : std_logic;
+               signal pc_busy : std_logic;
                signal rx_data, tx_data : std_logic_vector(7 downto 0);
 
                signal pc_zeile : hzeile;
@@ -52,6 +53,7 @@ begin
                pc_spalte => pc_spalte,
                pc_get => pc_get,
                pc_done => pc_done,
+               pc_busy => pc_busy,
                pc_char => pc_char
        );
 
@@ -65,16 +67,15 @@ begin
 
        stub_history : process
                file f : text open read_mode is "../../src/pc_communication.test";
-               --variable rb : hbyte;
                variable rb : character;
                variable good : boolean;
                variable i : integer;
                variable buf : my_string;
                variable l : line;
        begin
-               --take control of the situation.
                pc_char <= (others => '0');
                pc_done <= '0';
+               pc_busy <= '0';
                wait until sys_res_n = '1';
 
                while not endfile (f) loop
@@ -84,14 +85,16 @@ begin
                        while i < l'length loop
                                pc_done <= '0';
                                wait until rising_edge(pc_get);
+                               wait for 90 ns;
+                               pc_busy <= '1';
                                pc_char <= (others => '0');
                                wait for 300 ns;
 
                                pc_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
                                i := i + 1;
+                               pc_busy <= '0';
                                pc_done <= '1';
                                wait for 30 ns;
-                               
                        end loop;
                end loop;
 
@@ -116,16 +119,16 @@ begin
                -- init & reset
                -- we only simulate pressing of button a by now!
                sys_res_n <= '0';
-               btn_a <= '0';
+               btn_a <= '1';
                rx_data <= ( others => '0');
                rx_new <= '0';
                
                wait for 90 ns;
                sys_res_n <= '1';
                wait for 30 ns;
-               btn_a <= '1';
-               wait for 30 ns;
                btn_a <= '0';
+               wait for 30 ns;
+               btn_a <= '1';
                wait;
                --wait for 1000 ns;
                --assert false report "test beendet" severity failure;