removed unresolvedness of some signals and multiple sources

[hwmod.git] / src / beh_pc_communication_tb.vhd

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index 4efc777a9f1a4895ee5fa0d328b113ae9e9591bc..1ed8b7585a490225ee86ae6e704711975191a9d2 100644 (file)
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -66,29 +66,39 @@ begin
                file f : byte_file_type open read_mode is "../../src/pc_communication.test";
                variable rb : hbyte;
        begin
+               d_done <= '0';
                wait until rising_edge(d_get);
                assert not endfile(f) report "test beendet" severity failure;
                read(f, rb);
                wait for 30 ns;
                d_char <= rb;
                d_done <= '1';
-               wait for 15 ns;
-               d_done <= '0';
+               wait for 30 ns;
        end process stub_history;
 
+
+       stub_uart : process
+       begin
+               tx_done <= '0';
+               wait until rising_edge(tx_new);
+               wait for 90 ns;
+               tx_done <= '1'; -- FIXME: why is this unresolved?
+               wait for 30 ns;
+       end process stub_uart;
+
        reset_and_button : process
        begin
                -- init & reset
                -- we only simulate pressing of button a by now!
                sys_res_n <= '0';
                btn_a <= '0';
-               d_done <= '0';
                tx_data <= "00000000";
                rx_data <= "00000000";
                d_zeile <= "0000000";
                d_spalte <= "0000000";
-               tx_new <= '0';
                tx_done <= '0';
+               rx_new <= '0';
+               d_char <= (others => '0');
                
                wait for 90 ns;
                sys_res_n <= '1';
@@ -96,7 +106,9 @@ begin
                btn_a <= '1';
                wait for 15 ns;
                btn_a <= '0';
-               wait;
+               --wait;
+               wait for 1000 ns;
+               assert false report "test beendet" severity failure;
        end process reset_and_button;
 
 end architecture sim;