fixed processes to be never rerunning an use loops instead, this makes the code less...

[hwmod.git] / src / beh_pc_communication_tb.vhd

diff --git a/src/beh_pc_communication_tb.vhd b/src/beh_pc_communication_tb.vhd
index 1ed8b7585a490225ee86ae6e704711975191a9d2..0775e5e28f8915c8a4b8286f23beaa7cc8663ae1 100644 (file)
--- a/src/beh_pc_communication_tb.vhd
+++ b/src/beh_pc_communication_tb.vhd
@@ -14,6 +14,7 @@ end entity beh_pc_communication_tb;
 
 architecture sim of beh_pc_communication_tb is
                type byte_file_type is file of hbyte;
+               subtype my_string is string(1 to 720);
                signal sys_clk : std_logic;
                signal sys_res_n : std_logic;
                signal btn_a : std_logic;
@@ -63,27 +64,49 @@ begin
        end process clk;
 
        stub_history : process
-               file f : byte_file_type open read_mode is "../../src/pc_communication.test";
-               variable rb : hbyte;
+               file f : text open read_mode is "../../src/pc_communication.test";
+               --variable rb : hbyte;
+               variable rb : character;
+               variable good : boolean;
+               variable i : integer;
+               variable buf : my_string;
+               variable l : line;
        begin
-               d_done <= '0';
-               wait until rising_edge(d_get);
+               --take control of the situation.
+               d_char <= (others => '0');
+               wait until sys_res_n = '1';
+
+               while not endfile (f) loop
+                       readline(f, l);
+                       i := 1;
+                       while i < l'length loop
+                               wait until rising_edge(d_get);
+                               d_done <= '0';
+                               d_char <= (others => '0');
+                               wait for 90 ns;
+
+                               d_char <= hbyte(std_logic_vector(to_unsigned(character'pos(buf(i)),8)));
+                               d_done <= '1';
+                               wait for 30 ns;
+                               
+                       end loop;
+               end loop;
+
                assert not endfile(f) report "test beendet" severity failure;
-               read(f, rb);
-               wait for 30 ns;
-               d_char <= rb;
-               d_done <= '1';
-               wait for 30 ns;
        end process stub_history;
 
-
        stub_uart : process
        begin
                tx_done <= '0';
-               wait until rising_edge(tx_new);
-               wait for 90 ns;
-               tx_done <= '1'; -- FIXME: why is this unresolved?
-               wait for 30 ns;
+               while true loop
+                       wait until sys_res_n = '1';
+
+                       wait until rising_edge(tx_new);
+                       tx_done <= '0';
+                       wait for 300 ns;
+                       tx_done <= '1';
+                       wait for 30 ns;
+               end loop;
        end process stub_uart;
 
        reset_and_button : process
@@ -92,13 +115,11 @@ begin
                -- we only simulate pressing of button a by now!
                sys_res_n <= '0';
                btn_a <= '0';
-               tx_data <= "00000000";
-               rx_data <= "00000000";
-               d_zeile <= "0000000";
-               d_spalte <= "0000000";
-               tx_done <= '0';
+               tx_data <= ( others => '0');
+               rx_data <= ( others => '0');
+               d_zeile <= ( others => '0');
+               d_spalte <= ( others => '0');
                rx_new <= '0';
-               d_char <= (others => '0');
                
                wait for 90 ns;
                sys_res_n <= '1';
@@ -106,9 +127,9 @@ begin
                btn_a <= '1';
                wait for 15 ns;
                btn_a <= '0';
-               --wait;
-               wait for 1000 ns;
-               assert false report "test beendet" severity failure;
+               wait;
+               --wait for 1000 ns;
+               --assert false report "test beendet" severity failure;
        end process reset_and_button;
 
 end architecture sim;