uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / beh_parser_tb.vhd

diff --git a/src/beh_parser_tb.vhd b/src/beh_parser_tb.vhd
index cb4c5b5c21188f5fa0756f69955ff4e8d1bcfd6d..6b3f9e6d414d6b82d82cbca224592a138156bf7e 100644 (file)
--- a/src/beh_parser_tb.vhd
+++ b/src/beh_parser_tb.vhd
@@ -10,22 +10,19 @@ architecture sim of beh_parser_tb is
        -- system
        signal sys_clk, sys_res_n : std_logic;
        -- history
-       signal p_rw, p_rget, p_rdone, p_wtake, p_wdone, p_finished : std_logic;
+       signal p_rget, p_rdone, p_wtake, p_wdone, p_finished : std_logic;
        signal p_read, p_write : hbyte;
-       signal p_spalte : hspalte;
        --scanner
        signal do_it : std_logic;
        signal finished : std_logic;
 
        signal stop : boolean := false;
 begin
-       inst : entity work.parser(beh)
-       port map
-       (
+       inst : parser
+       port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
-               p_rw => p_rw,
-               p_spalte => p_spalte,
+               -- history
                p_rget => p_rget,
                p_rdone => p_rdone,
                p_read => p_read,
@@ -76,12 +73,12 @@ begin
 
                i := 1;
                f_loop : while not endfile(f) loop
-                       realresult := (72 => nul, others => ' ');
+                       realresult := (HSPALTE_MAX+1 => nul, others => ' ');
 
                        f1_loop : while not endfile(f) loop
                                readline (f, l);
                                input := (others => nul);
-                               if (l'length <= 72) then
+                               if (l'length <= HSPALTE_MAX+1) then
                                        input(1 to l'length) := l.all;
                                        if (input(1) = '#') then
                                                next f1_loop;
@@ -97,7 +94,7 @@ begin
                        f2_loop : while not endfile(f) loop
                                readline (f, l);
                                expectedresult := (others => nul);
-                               if (l'length <= 72) then
+                               if (l'length <= HSPALTE_MAX+1) then
                                        expectedresult(1 to l'length) := l.all;
                                        if (expectedresult(1) = '#') then
                                                next f2_loop;
@@ -113,10 +110,10 @@ begin
 
                        -- ergebnis string richtig formatieren
                        hstrtmp := expectedresult;
-                       expectedresult := (72 => nul, others => ' ');
-                       for x in 1 to 71 loop
+                       expectedresult := (HSPALTE_MAX+1 => nul, others => ' ');
+                       for x in 1 to HSPALTE_MAX loop
                                if hstrtmp(x) /= nul then
-                                       expectedresult((71-y) + x) := hstrtmp(x);
+                                       expectedresult((HSPALTE_MAX-y) + x) := hstrtmp(x);
                                end if;
                        end loop;
 
@@ -128,7 +125,7 @@ begin
                        icwait(sys_clk, 5);
                        do_it <= '1';
                        run_tc := true;
-                       j := 1; k := 71;
+                       j := 1; k := HSPALTE_MAX;
 
                        while run_tc loop
                                wait on p_rget, p_wtake, p_finished, finished;