-- alu
signal opcode : alu_ops;
- signal op1, op2, op3 : csigned;
+ signal op1, op2, op3, opM : csigned;
signal do_calc, calc_done, calc_error : std_logic;
--scanner
op1 => op1,
op2 => op2,
op3 => op3,
+ opM => opM,
do_calc => do_calc,
calc_done => calc_done,
calc_error => calc_error,
op1 => op1,
op2 => op2,
op3 => op3,
+ opM => opM,
opcode => opcode
);
i := 1;
f_loop : while not endfile(f) loop
- realresult := (71 => character'val(0), others => character'val(32));
+ realresult := (71 => nul, others => ' ');
f1_loop : while not endfile(f) loop
readline (f, l);
- input := (others => character'val(0));
+ input := (others => nul);
if (l'length <= 72) then
input(1 to l'length) := l.all;
if (input(1) = '#') then
f2_loop : while not endfile(f) loop
readline (f, l);
- expectedresult := (others => character'val(0));
+ expectedresult := (others => nul);
if (l'length <= 72) then
expectedresult(1 to l'length) := l.all;
if (expectedresult(1) = '#') then
-- ergebnis string richtig formatieren
hstrtmp := expectedresult;
- expectedresult := (71 => character'val(0), others => character'val(32));
+ expectedresult := (71 => nul, others => ' ');
for x in 1 to 70 loop
- if hstrtmp(x) /= character'val(0) then
+ if hstrtmp(x) /= nul then
expectedresult((70-y) + x) := hstrtmp(x);
end if;
end loop;