uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / beh_loopback_tb.vhd

diff --git a/src/beh_loopback_tb.vhd b/src/beh_loopback_tb.vhd
index a44bdbdadbdb5823eafb07ddbed032a48755a66f..4bc01c8a38e8b4fa965796ef33ba08aaba594da8 100644 (file)
--- a/src/beh_loopback_tb.vhd
+++ b/src/beh_loopback_tb.vhd
@@ -17,7 +17,7 @@ architecture sim of beh_loopback_tb is
        signal tx_data : std_logic_vector (7 downto 0);
        signal stop : boolean := false;
 begin
-       inst_rx : entity work.uart_rx(beh)
+       inst_rx : uart_rx
        generic map (
                CLK_FREQ => CLK_FREQ,
                BAUDRATE => BAUDRATE
@@ -29,7 +29,7 @@ begin
                rx_data => rx_data,
                rx_new => rx_new
        );
-       inst_tx : entity work.uart_tx(beh)
+       inst_tx : uart_tx
        generic map (
                CLK_FREQ => CLK_FREQ,
                BAUDRATE => BAUDRATE
@@ -99,12 +99,12 @@ begin
                -- 1. parameter: testfallnummer
                -- 2. parameter: STARTBIT (1 bit) - immer '0' | 8 DATENBITS | 1 STOPBIT - immer '1'
                -- 3. parameter: byte das rauskommen soll
-               exec_tc(1, b"0000011111", b"00001111");
-               exec_tc(2, b"0101010101", b"10101010");
-               exec_tc(3, b"0110011001", b"11001100");
-               exec_tc(4, b"0001100111", b"00110011");
-               exec_tc(5, b"0010101011", b"01010101");
-               exec_tc(6, b"0100110111", b"10011011");
+               exec_tc(1, b"0000011111", b"11110000");
+               exec_tc(2, b"0101010101", b"01010101");
+               exec_tc(3, b"0110011001", b"00110011");
+               exec_tc(4, b"0001100111", b"11001100");
+               exec_tc(5, b"0010101011", b"10101010");
+               exec_tc(6, b"0100110111", b"11011001");
 
                stop <= true;
                wait;