signal pc_spalte : hspalte;
signal pc_get, pc_done : std_logic;
signal pc_char : hbyte;
- signal pc_busy : std_logic;
--dummy button
signal btn_a_int : std_logic;
- --output beautifier
- signal tx_debug : character;
-
signal stop : boolean := false;
begin
-- history
- inst : entity work.history(beh)
+ inst : history
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n,
pc_spalte => pc_spalte,
pc_zeile => pc_zeile,
pc_char => pc_char,
- pc_busy => pc_busy,
pc_done => pc_done
);
-- display
- inst_disp : entity work.display(beh)
+ inst_disp : display
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n,
);
-- parser
- inst_parser : entity work.parser(beh)
+ inst_parser : parser
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n,
);
-- scanner
- inst_scan : entity work.scanner(beh)
+ inst_scan : scanner
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n,
finished => finished
);
--uart_tx
- inst_uart : entity work.uart_tx(beh)
+ inst_uart : uart_tx
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n,
);
--pc_communication
- inst_pc_com : entity work.pc_communication(beh)
+ inst_pc_com : pc_communication
port map(
sys_clk => sys_clk,
sys_res_n => sys_res_n,
pc_spalte => pc_spalte,
pc_get => pc_get,
pc_done => pc_done,
- pc_char => pc_char,
- pc_busy => pc_busy
+ pc_char => pc_char
);
- tx_debug <= character'val(to_integer(unsigned(tx_data)));
process
begin
report "==================";
end loop f_loop;
- icwait(sys_clk, 850);
+ -- uart ist ziemlich langsam...
+ icwait(sys_clk, 1000000000);
stop <= true;
wait;
end process;
begin
btn_a_int <= '1';
wait until sys_res_n = '1';
- wait for 50000 * 15 ns;
+ icwait(sys_clk, 50000);
wait until rising_edge(sys_clk);
btn_a_int <= '0';
wait for 30 ns;