use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gen_pkg.all;
+use work.textmode_vga_component_pkg.all;
+use work.textmode_vga_pkg.all;
+use work.textmode_vga_platform_dependent_pkg.all;
entity beh_history_tb is
end entity beh_history_tb;
-- system
signal sys_clk, sys_res_n : std_logic;
-- history/display
- signal d_new_eingabe, d_new_result : std_logic;
+ signal d_new_eingabe, d_new_result, d_new_bs : std_logic;
signal d_zeile : hzeile;
signal d_spalte : hspalte;
signal d_get, d_done : std_logic;
-- history/scanner
signal s_char : hbyte;
signal s_take, s_done, s_backspace : std_logic;
-
- -- tmp: history<>scanner
+ -- ps/2
+ signal new_data : std_logic;
+ signal data : std_logic_vector(7 downto 0);
+ -- vga/display
+ signal free : std_logic;
+ signal command : std_logic_vector(COMMAND_SIZE - 1 downto 0);
+ signal command_data : std_logic_vector(3 * COLOR_SIZE + CHAR_SIZE -1 downto 0);
+ -- history/parser
+ signal p_rget : std_logic;
+ signal p_rdone : std_logic;
+ signal p_read : hbyte;
+ signal p_wtake : std_logic;
+ signal p_wdone : std_logic;
+ signal p_write : hbyte;
+ signal p_finished : std_logic;
+ -- parser/scanner
signal do_it, finished : std_logic;
+ --uart_tx
+ signal tx_data : std_logic_vector(7 downto 0);
+ signal tx_new, tx_done, txd : std_logic;
+ --pc_communication
+ signal pc_zeile : hzeile;
+ signal pc_spalte : hspalte;
+ signal pc_get, pc_done : std_logic;
+ signal pc_char : hbyte;
+ --dummy button
+ signal btn_a_int : std_logic;
signal stop : boolean := false;
begin
-- history
- inst : entity work.history(beh)
+ inst : history
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n,
-- display
d_new_eingabe => d_new_eingabe,
d_new_result => d_new_result,
+ d_new_bs => d_new_bs,
d_zeile => d_zeile,
d_spalte => d_spalte,
d_get => d_get,
d_done => d_done,
d_char => d_char,
- -- TODO: tmp only!
+ -- parser
+ p_rget => p_rget,
+ p_rdone => p_rdone,
+ p_read => p_read,
+ p_wtake => p_wtake,
+ p_wdone => p_wdone,
+ p_write => p_write,
+ p_finished => p_finished,
+ -- PC-komm
+ pc_get => pc_get,
+ pc_spalte => pc_spalte,
+ pc_zeile => pc_zeile,
+ pc_char => pc_char,
+ pc_done => pc_done
+ );
+
+ -- display
+ inst_disp : display
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ -- history
+ d_new_eingabe => d_new_eingabe,
+ d_new_result => d_new_result,
+ d_new_bs => d_new_bs,
+ d_zeile => d_zeile,
+ d_spalte => d_spalte,
+ d_get => d_get,
+ d_done => d_done,
+ d_char => d_char,
+ -- vga
+ command => command,
+ command_data => command_data,
+ free => free
+ );
+
+ -- parser
+ inst_parser : parser
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ -- history
+ p_rget => p_rget,
+ p_rdone => p_rdone,
+ p_read => p_read,
+ p_wtake => p_wtake,
+ p_wdone => p_wdone,
+ p_write => p_write,
+ p_finished => p_finished,
+ -- scanner
do_it => do_it,
finished => finished
);
+ -- scanner
+ inst_scan : scanner
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ -- ps/2
+ new_data => new_data,
+ data => data,
+ -- history
+ s_char => s_char,
+ s_take => s_take,
+ s_done => s_done,
+ s_backspace => s_backspace,
+ -- Parser
+ do_it => do_it,
+ finished => finished
+ );
+ --uart_tx
+ inst_uart : uart_tx
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ txd => txd,
+ tx_data =>tx_data,
+ tx_new => tx_new,
+ tx_done => tx_done
+ );
+
+ --pc_communication
+ inst_pc_com : pc_communication
+ port map(
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ --button
+ btn_a => btn_a_int,
+ --uart_tx
+ tx_data => tx_data,
+ tx_new => tx_new,
+ tx_done => tx_done,
+ --uart_rx
+ rx_data => (others => '0'),
+ rx_new => '0',
+ -- History
+ pc_zeile => pc_zeile,
+ pc_spalte => pc_spalte,
+ pc_get => pc_get,
+ pc_done => pc_done,
+ pc_char => pc_char
+ );
+
process
begin
sys_clk <= '0';
end process;
process
- variable input : hstring := "12345678 ";
- variable ctmp : character;
+ begin
+ free <= '0';
+ wait for 15 ns;
+ free <= '1';
+ wait for 30 ns;
+ if stop = true then
+ wait;
+ end if;
+ end process;
+
+ process
+ -- textio stuff
+ use std.textio.all;
+ file f : text open read_mode is "../../src/history.test";
+ variable l : line;
+
+ variable input : string(1 to 100);
- variable checkall : boolean := true;
- variable i : integer := 1;
- variable j : integer;
+ variable run_tc, run_inner : boolean := true;
+ variable i, j, y : natural;
begin
-- init & reset
sys_res_n <= '0';
- s_char <= x"00";
- s_take <= '0';
- s_backspace <= '0';
- d_zeile <= (others => '0');
- d_spalte <= (others => '0');
- d_get <= '0';
- do_it <= '0';
-
- icwait(sys_clk, 5);
+ new_data <= '0';
+ data <= (others => '0');
+
+ icwait(sys_clk, 20);
sys_res_n <= '1';
- while i <= 10 loop
- s_take <= '1';
- ctmp := input(i);
- s_char <= hbyte(to_unsigned(character'pos(ctmp),8));
- wait on s_done;
- s_take <= '0';
- wait on d_new_eingabe;
- icwait(sys_clk, 2);
- j := 1;
- while j <= i loop
- d_spalte <= std_logic_vector(to_unsigned(j,7));
- d_zeile <= (others => '0');
- d_get <= '1';
- wait on d_done;
- icwait(sys_clk, 1);
- if d_char /= hbyte(to_unsigned(character'pos(input(j)),8)) then
- assert(false) report "passt nicht? d_char: "
- & character'val(to_integer(unsigned(d_char))) & ", solte sein: "
- & input(j);
- checkall := false;
+ i := 1;
+ f_loop : while not endfile(f) loop
+ data <= (others => '0');
+
+ f1_loop : while not endfile(f) loop
+ readline (f, l);
+ input := (others => nul);
+ if (l'length <= 100) then
+ input(1 to l'length) := l.all;
+ if (input(1) = '#') then
+ next f1_loop;
+ else
+ exit f1_loop;
+ end if;
+ else
+ report "fehler in history.test: eingabe zu lange in testfall " & natural'image(i);
+ next f_loop;
end if;
- d_get <= '0';
- icwait(sys_clk, 2);
- j := j + 1;
- end loop;
+ end loop f1_loop;
+
+ report "testcase(" & natural'image(i) & ").input: " & input;
i := i + 1;
- end loop;
- do_it <= '1';
- wait on finished;
- icwait(sys_clk, 2);
- do_it <= '0';
+ icwait(sys_clk, 5);
+ run_tc := true;
+ j := 0;
+ mainl : while run_tc loop
+ icwait(sys_clk, 10);
+ j := j + 1;
- if checkall then
- report "alle testfaelle der History waren erfolgreich!";
- else
- report "einige testfaelle schlugen fehl";
- end if;
- icwait(sys_clk, 10);
+ if j = 101 then
+ run_tc := false;
+ assert(false) report "wtf @ schleife";
+ next mainl;
+ end if;
+
+ new_data <= '1';
+
+ case input(j) is
+ when nul => data <= ascii2sc(x"1c"); -- $ (enter)
+ when '!' => data <= ascii2sc(x"0e"); -- ! (backspace)
+ when '/' =>
+ data <= x"e0";
+ icwait(sys_clk, 1);
+ new_data <= '0';
+ icwait(sys_clk, 1);
+ new_data <= '1';
+ data <= SC_KP_DIV;
+ when others => data <= ascii2sc(std_logic_vector(to_unsigned(character'pos(input(j)),8)));
+ end case;
+
+ -- ack'en skippen, falls es ein "spezielles" zeichen ist (steht
+ -- in abhaengigkeit zum vorherigen zeichen)
+ if(not valid_char(data)) then
+ next mainl;
+ end if;
+
+ -- wuenschswert waere das hier:
+ -- > wait on s_backspace, s_take, do_it;
+ -- geht aber leider nicht, weil sich die signale vllt schon
+ -- geaendert haben
+ run_inner := true;
+ main_inner : while run_inner loop
+ icwait(sys_clk, 1);
+
+ run_inner := false;
+ if s_backspace = '1' or s_take = '1' then
+ icwait(sys_clk, 1);
+ wait on s_take; -- = '0'
+ icwait(sys_clk, 1);
+ elsif do_it = '1' then
+ -- dauert normalweiser noch laenger (parser braucht
+ -- relativ lange)
+ icwait(sys_clk, 7);
+ wait on do_it; -- = '0'
+ icwait(sys_clk, 850);
+
+ run_tc := false;
+ else
+ -- assert(false) report "history_tb: kann passieren. wenn tb haengt, dann hier auskommentieren";
+ run_inner := true;
+ end if;
+ end loop;
+ end loop;
+ report "==================";
+ end loop f_loop;
+
+ -- uart ist ziemlich langsam...
+ icwait(sys_clk, 1000000000);
stop <= true;
wait;
end process;
+
+ btn_pressed : process is
+ begin
+ btn_a_int <= '1';
+ wait until sys_res_n = '1';
+ icwait(sys_clk, 50000);
+ wait until rising_edge(sys_clk);
+ btn_a_int <= '0';
+ wait for 30 ns;
+ btn_a_int <= '1';
+ wait;
+ end process btn_pressed;
end architecture sim;
projects / hwmod.git / blobdiff