signal p_finished : std_logic;
-- parser/scanner
signal do_it, finished : std_logic;
+ --uart_tx
+ signal tx_data : std_logic_vector(7 downto 0);
+ signal tx_new, tx_done, txd : std_logic;
+ --pc_communication
+ signal pc_zeile : hzeile;
+ signal pc_spalte : hspalte;
+ signal pc_get, pc_done : std_logic;
+ signal pc_char : hbyte;
+ --dummy button
+ signal btn_a_int : std_logic;
signal stop : boolean := false;
begin
-- history
- inst : entity work.history(beh)
+ inst : history
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n,
p_wtake => p_wtake,
p_wdone => p_wdone,
p_write => p_write,
- p_finished => p_finished
+ p_finished => p_finished,
+ -- PC-komm
+ pc_get => pc_get,
+ pc_spalte => pc_spalte,
+ pc_zeile => pc_zeile,
+ pc_char => pc_char,
+ pc_done => pc_done
);
-- display
- inst_disp : entity work.display(beh)
+ inst_disp : display
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n,
);
-- parser
- inst_parser : entity work.parser(beh)
+ inst_parser : parser
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n,
);
-- scanner
- inst_scan : entity work.scanner(beh)
+ inst_scan : scanner
port map (
sys_clk => sys_clk,
sys_res_n => sys_res_n,
do_it => do_it,
finished => finished
);
+ --uart_tx
+ inst_uart : uart_tx
+ port map (
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ txd => txd,
+ tx_data =>tx_data,
+ tx_new => tx_new,
+ tx_done => tx_done
+ );
+ --pc_communication
+ inst_pc_com : pc_communication
+ port map(
+ sys_clk => sys_clk,
+ sys_res_n => sys_res_n,
+ --button
+ btn_a => btn_a_int,
+ --uart_tx
+ tx_data => tx_data,
+ tx_new => tx_new,
+ tx_done => tx_done,
+ --uart_rx
+ rx_data => (others => '0'),
+ rx_new => '0',
+ -- History
+ pc_zeile => pc_zeile,
+ pc_spalte => pc_spalte,
+ pc_get => pc_get,
+ pc_done => pc_done,
+ pc_char => pc_char
+ );
process
begin
report "==================";
end loop f_loop;
- icwait(sys_clk, 850);
+ -- uart ist ziemlich langsam...
+ icwait(sys_clk, 1000000000);
stop <= true;
wait;
end process;
+
+ btn_pressed : process is
+ begin
+ btn_a_int <= '1';
+ wait until sys_res_n = '1';
+ icwait(sys_clk, 50000);
+ wait until rising_edge(sys_clk);
+ btn_a_int <= '0';
+ wait for 30 ns;
+ btn_a_int <= '1';
+ wait;
+ end process btn_pressed;
end architecture sim;