uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / beh_history_tb.vhd

diff --git a/src/beh_history_tb.vhd b/src/beh_history_tb.vhd
index 2a24d04d7313a59d00791a0e07a69e1cd7ef6bf4..f249361c03d3f9869e405015187fe99d630ecb42 100644 (file)
--- a/src/beh_history_tb.vhd
+++ b/src/beh_history_tb.vhd
@@ -49,11 +49,10 @@ architecture sim of beh_history_tb is
        --dummy button
        signal btn_a_int : std_logic;
 
-
        signal stop : boolean := false;
 begin
        -- history
-       inst : entity work.history(beh)
+       inst : history
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
@@ -88,7 +87,7 @@ begin
        );
 
        -- display
-       inst_disp : entity work.display(beh)
+       inst_disp : display
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
@@ -108,7 +107,7 @@ begin
        );
 
        -- parser
-       inst_parser : entity work.parser(beh)
+       inst_parser : parser
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
@@ -126,7 +125,7 @@ begin
        );
 
        -- scanner
-       inst_scan : entity work.scanner(beh)
+       inst_scan : scanner
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
@@ -143,7 +142,7 @@ begin
                finished => finished
        );
        --uart_tx
-       inst_uart : entity work.uart_tx(beh)
+       inst_uart : uart_tx
        port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
@@ -154,7 +153,7 @@ begin
        );
 
        --pc_communication
-       inst_pc_com : entity work.pc_communication(beh)
+       inst_pc_com : pc_communication
        port map(
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
@@ -168,11 +167,11 @@ begin
                rx_data => (others => '0'),
                rx_new => '0',
                -- History
-                pc_zeile  => pc_zeile,
-                pc_spalte => pc_spalte,
-                pc_get    => pc_get,
-                pc_done   => pc_done,
-                pc_char   => pc_char
+               pc_zeile  => pc_zeile,
+               pc_spalte => pc_spalte,
+               pc_get    => pc_get,
+               pc_done   => pc_done,
+               pc_char   => pc_char
        );
 
        process
@@ -304,20 +303,21 @@ begin
                        report "==================";
                end loop f_loop;
 
-               icwait(sys_clk, 850);
+               -- uart ist ziemlich langsam...
+               icwait(sys_clk, 1000000000);
                stop <= true;
                wait;
        end process;
 
        btn_pressed : process is
        begin
-               btn_a_int <= '0';
+               btn_a_int <= '1';
                wait until sys_res_n = '1';
-               wait for 50000 * 15 ns;
+               icwait(sys_clk, 50000);
                wait until rising_edge(sys_clk);
-               btn_a_int <= '1';
-               wait for 30 ns;
                btn_a_int <= '0';
+               wait for 30 ns;
+               btn_a_int <= '1';
                wait;
        end process btn_pressed;
 end architecture sim;