pc_com: p_busy ist unnoetig und noch ein paar kleinere fehler ausgebessert

[hwmod.git] / src / beh_history_tb.vhd

diff --git a/src/beh_history_tb.vhd b/src/beh_history_tb.vhd
index abce49d9826eadf770228f27b85bbf478fd8859f..87115c724c2ed37b7ed3faa0634838bea4ee4250 100644 (file)
--- a/src/beh_history_tb.vhd
+++ b/src/beh_history_tb.vhd
@@ -49,7 +49,6 @@ architecture sim of beh_history_tb is
        --dummy button
        signal btn_a_int : std_logic;
 
-
        signal stop : boolean := false;
 begin
        -- history
@@ -168,11 +167,11 @@ begin
                rx_data => (others => '0'),
                rx_new => '0',
                -- History
-                d_zeile  => pc_zeile,
-                d_spalte => pc_spalte,
-                d_get    => pc_get,
-                d_done   => pc_done,
-                d_char   => pc_char
+               pc_zeile  => pc_zeile,
+               pc_spalte => pc_spalte,
+               pc_get    => pc_get,
+               pc_done   => pc_done,
+               pc_char   => pc_char
        );
 
        process
@@ -304,20 +303,21 @@ begin
                        report "==================";
                end loop f_loop;
 
-               icwait(sys_clk, 850);
+               -- uart ist ziemlich langsam...
+               icwait(sys_clk, 1000000000);
                stop <= true;
                wait;
        end process;
 
        btn_pressed : process is
        begin
-               btn_a_int <= '0';
+               btn_a_int <= '1';
                wait until sys_res_n = '1';
-               wait for 50000 * 15 ns;
+               icwait(sys_clk, 50000);
                wait until rising_edge(sys_clk);
-               btn_a_int <= '1';
-               wait for 30 ns;
                btn_a_int <= '0';
+               wait for 30 ns;
+               btn_a_int <= '1';
                wait;
        end process btn_pressed;
 end architecture sim;