alu: weniger logic elemente dafuer mehr taktzyklen noetig (= egal)

[hwmod.git] / src / beh_alu_tb.vhd

diff --git a/src/beh_alu_tb.vhd b/src/beh_alu_tb.vhd
index 15bb002cb2cb36f210366ad0db98dc6d6eea9143..f6c6d5b3918ed1620a30102c0013d286c371f3e1 100644 (file)
--- a/src/beh_alu_tb.vhd
+++ b/src/beh_alu_tb.vhd
@@ -119,6 +119,8 @@ begin
                          61 => (-2147483647, ALU_SUB, 1, 0, -2147483648, false),
                          62 => (-2147483647, ALU_ADD, -1, 0, -2147483648, false),
                          63 => (-2147483648, ALU_DIV, 10, 8, -214748364, false),
+                         64 => (-214748364, ALU_DIV, 10, 4, -21474836, false),
+                         65 => (1, ALU_DIV, -2147483648, 1, 0, false),
                          others => (0, ALU_ADD, 0, 0, 0, false)
                        );
                variable checkall : boolean := true;