uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / beh_alu_tb.vhd

diff --git a/src/beh_alu_tb.vhd b/src/beh_alu_tb.vhd
index aba54cb514cb1fdde1edd792e4c49ed0e6206323..96cbeebca2ea642cac93e36714a9a6068a4b88fb 100644 (file)
--- a/src/beh_alu_tb.vhd
+++ b/src/beh_alu_tb.vhd
@@ -12,9 +12,8 @@ architecture sim of beh_alu_tb is
        signal op1, op2, op3, opM : csigned;
        signal stop : boolean := false;
 begin
-       inst : entity work.alu(beh)
-       port map
-       (
+       inst : alu
+       port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
                do_calc => do_calc,
@@ -116,6 +115,11 @@ begin
                          56 => (5134123, ALU_DIV, 358015, 121913, 14, false),
                          -- extra
                          60 => (5, ALU_SUB, -2147483648, 0, 0, true),
+                         61 => (-2147483647, ALU_SUB, 1, 0, -2147483648, false),
+                         62 => (-2147483647, ALU_ADD, -1, 0, -2147483648, false),
+                         63 => (-2147483648, ALU_DIV, 10, 8, -214748364, false),
+                         64 => (-214748364, ALU_DIV, 10, 4, -21474836, false),
+                         65 => (1, ALU_DIV, -2147483648, 1, 0, false),
                          others => (0, ALU_ADD, 0, 0, 0, false)
                        );
                variable checkall : boolean := true;
@@ -159,8 +163,8 @@ begin
                                        assert(false) report "testfall war ein error (passt)";
                                end if;
                        else
-                               assert ((op3 = to_signed(testmatrix(i).expected,CBITS)) and (opM = to_signed(testmatrix(i).om,CBITS)))
-                                       report "" & cinteger'image(testmatrix(i).o1) & 
+                               if not((op3 = to_signed(testmatrix(i).expected,CBITS)) and (opcode /= ALU_DIV or opM = to_signed(testmatrix(i).om,CBITS))) then
+                                       assert(false) report "" & cinteger'image(testmatrix(i).o1) & 
                                        " " & integer'image(to_integer(signed(opcode))) &
                                        " " & cinteger'image(testmatrix(i).o2) &
                                        " /= " & integer'image(to_integer(op3)) &
@@ -168,7 +172,6 @@ begin
                                        " -- erwartet: " & cinteger'image(testmatrix(i).expected) &
                                        " ( " & cinteger'image(testmatrix(i).om) & " ) ";
 
-                               if not((op3 = to_signed(testmatrix(i).expected,CBITS)) and (opM = to_signed(testmatrix(i).om,CBITS))) then
                                        checkall := false;
                                end if;
                        end if;