uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / beh_alu_tb.vhd

diff --git a/src/beh_alu_tb.vhd b/src/beh_alu_tb.vhd
index 15bb002cb2cb36f210366ad0db98dc6d6eea9143..96cbeebca2ea642cac93e36714a9a6068a4b88fb 100644 (file)
--- a/src/beh_alu_tb.vhd
+++ b/src/beh_alu_tb.vhd
@@ -12,9 +12,8 @@ architecture sim of beh_alu_tb is
        signal op1, op2, op3, opM : csigned;
        signal stop : boolean := false;
 begin
-       inst : entity work.alu(beh)
-       port map
-       (
+       inst : alu
+       port map (
                sys_clk => sys_clk,
                sys_res_n => sys_res_n,
                do_calc => do_calc,
@@ -119,6 +118,8 @@ begin
                          61 => (-2147483647, ALU_SUB, 1, 0, -2147483648, false),
                          62 => (-2147483647, ALU_ADD, -1, 0, -2147483648, false),
                          63 => (-2147483648, ALU_DIV, 10, 8, -214748364, false),
+                         64 => (-214748364, ALU_DIV, 10, 4, -21474836, false),
+                         65 => (1, ALU_DIV, -2147483648, 1, 0, false),
                          others => (0, ALU_ADD, 0, 0, 0, false)
                        );
                variable checkall : boolean := true;