parser: ausdruecke werden erfolgreich geparst, einschraenkungen:

[hwmod.git] / src / alu.vhd

diff --git a/src/alu.vhd b/src/alu.vhd
index 7a57b59229cd1ad6f63287f827c14e42bdc8d4ee..a1b7a41438e18ee6776ef3a5f9caf53b8b3bf041 100644 (file)
--- a/src/alu.vhd
+++ b/src/alu.vhd
@@ -23,7 +23,7 @@ architecture beh of alu is
        SDONE, SERROR);
        signal state_int, state_next : ALU_STATE;
        signal done_intern, error_intern, div_calc_done, div_go_calc : std_logic;
-       signal op3_int, op3_next : csigned := (others => '0');
+       signal op3_int, op3_next : csigned;
        signal calc_done_int, calc_done_next : std_logic;
        signal calc_error_int, calc_error_next : std_logic;
        -- signale fuer division
@@ -138,7 +138,7 @@ begin
                op1_next <= (others => '0');
                op2_next <= (others => '0');
                sign_next <= '0';
-               op3_next <= (others => '0');
+               op3_next <= op3_int;
 
                case state_int is
                        when SIDLE =>
@@ -170,7 +170,7 @@ begin
                                op3_next(CBITS-1) <= mulsign;
 
                                if mulsign = '1' then
-                                       multmp2 := not (multmp + 1);
+                                       multmp2 := (not multmp) + 1;
                                else
                                        multmp2 := multmp;
                                end if;
@@ -190,10 +190,10 @@ begin
                                        op1_var := op1;
                                        op2_var := op2;
                                        if op1(CBITS-1) = '1' then
-                                               op1_var := not (op1_var + 1);
+                                               op1_var := (not op1_var) + 1;
                                        end if;
                                        if op2(CBITS-1) = '1' then
-                                               op2_var := not (op2_var + 1);
+                                               op2_var := (not op2_var) + 1;
                                        end if;
 
                                        dividend_msb_var := find_msb(op1_var)-1;
@@ -243,7 +243,6 @@ begin
                                if (state_int = SERROR) then
                                        calc_error_next <= '1';
                                end if;
-                               op3_next <= op3_int;
                end case;
        end process;
 end architecture beh;