alu: error flag setzen bei overflow/underflow bzw. bei division durch 0

[hwmod.git] / src / alu.vhd

diff --git a/src/alu.vhd b/src/alu.vhd
index cdb9fdd44254ecd9d5815827c877455ee6b8325c..7a57b59229cd1ad6f63287f827c14e42bdc8d4ee 100644 (file)
--- a/src/alu.vhd
+++ b/src/alu.vhd
@@ -13,17 +13,19 @@ entity alu is
                op2 : in csigned;
                op3 : out csigned;
                do_calc : in std_logic;
-               calc_done : out std_logic
-               -- TODO: calc_error : out std_logic;
+               calc_done : out std_logic;
+               calc_error : out std_logic
        );
 end entity alu;
 
 architecture beh of alu is
-       type ALU_STATE is (SIDLE, SADD, SSUB, SMUL, SDIV, SDIV_CALC, SDIV_DONE, SDONE);
+       type ALU_STATE is (SIDLE, SADD, SSUB, SMUL, SDIV, SDIV_CALC, SDIV_DONE,
+       SDONE, SERROR);
        signal state_int, state_next : ALU_STATE;
-       signal done_intern, div_calc_done, div_go_calc : std_logic;
+       signal done_intern, error_intern, div_calc_done, div_go_calc : std_logic;
        signal op3_int, op3_next : csigned := (others => '0');
        signal calc_done_int, calc_done_next : std_logic;
+       signal calc_error_int, calc_error_next : std_logic;
        -- signale fuer division
        signal dividend_msb_int, dividend_msb_next, laengediv_int, laengediv_next : natural;
        signal quo_int, quo_next, aktdiv_int, aktdiv_int_next, op1_int, op1_next, op2_int, op2_next : csigned;
@@ -31,6 +33,7 @@ architecture beh of alu is
 begin
        op3 <= op3_int;
        calc_done <= calc_done_int;
+       calc_error <= calc_error_int;
 
        -- sync
        process(sys_clk, sys_res_n)
@@ -39,6 +42,7 @@ begin
                        state_int <= SIDLE;
                        op3_int <= (others => '0');
                        calc_done_int <= '0';
+                       calc_error_int <= '0';
                        --div
                        dividend_msb_int <= 0;
                        laengediv_int <= 0;
@@ -51,6 +55,7 @@ begin
                        state_int <= state_next;
                        op3_int <= op3_next;
                        calc_done_int <= calc_done_next;
+                       calc_error_int <= calc_error_next;
                        -- div
                        dividend_msb_int <= dividend_msb_next;
                        laengediv_int <= laengediv_next;
@@ -63,7 +68,8 @@ begin
        end process;
 
        -- next state
-       process(state_int, opcode, done_intern, do_calc, div_calc_done, div_go_calc)
+       process(state_int, opcode, done_intern, error_intern, do_calc,
+               div_calc_done, div_go_calc)
        begin
                -- set a default value for next state
                state_next <= state_int;
@@ -88,15 +94,21 @@ begin
                                if done_intern = '1' then
                                        state_next <= SDONE;
                                end if;
+                               if error_intern = '1' then
+                                       state_next <= SERROR;
+                               end if;
                        when SDIV =>
                                if div_go_calc = '1' then
                                        state_next <= SDIV_CALC;
                                end if;
+                               if error_intern = '1' then
+                                       state_next <= SERROR;
+                               end if;
                        when SDIV_CALC =>
                                if div_calc_done = '1' then
                                        state_next <= SDIV_DONE;
                                end if;
-                       when SDONE =>
+                       when SDONE | SERROR =>
                                if do_calc = '0' then
                                        state_next <= SIDLE;
                                end if;
@@ -105,15 +117,19 @@ begin
 
        -- output
        process(state_int, op1, op2, dividend_msb_int, laengediv_int, quo_int, aktdiv_int, sign_int, op1_int, op2_int, op3_int)
-               variable multmp : signed(((2*CBITS)-1) downto 0);
+               variable multmp, multmp2 : signed(((2*CBITS)-1) downto 0);
+               variable mulsign : std_logic;
+               variable tmp : csigned;
                -- vars fuer div
                variable laengediv_var, dividend_msb_var : natural;
                variable aktdiv_int_var, quo_var, op1_var, op2_var : csigned;
        begin
                calc_done_next <= '0';
+               calc_error_next <= '0';
                div_calc_done <= '0';
                div_go_calc <= '0';
                done_intern <= '0';
+               error_intern <= '0';
                -- default fuer div
                dividend_msb_next <= 0;
                laengediv_next <= 0;
@@ -128,21 +144,47 @@ begin
                        when SIDLE =>
                                null;
                        when SADD =>
-                               op3_next <= op1 + op2;
-                               done_intern <= '1';
+                               tmp := op1 + op2;
+                               op3_next <= tmp;
+
+                               -- over- bzw. underflow?
+                               if (op1(CBITS-1) = op2(CBITS-1)) and (op1(CBITS-1) /= tmp(CBITS -1)) then
+                                       error_intern <= '1';
+                               else
+                                       done_intern <= '1';
+                               end if;
                        when SSUB =>
-                               op3_next <= op1 - op2;
-                               done_intern <= '1';
+                               tmp := op1 - op2;
+                               op3_next <= tmp;
+
+                               -- over- bzw. underflow?
+                               if (op1(CBITS-1) /= op2(CBITS-1)) and (op1(CBITS-1) /= tmp(CBITS -1)) then
+                                       error_intern <= '1';
+                               else
+                                       done_intern <= '1';
+                               end if;
                        when SMUL =>
+                               mulsign := op1(CBITS-1) xor op2(CBITS-1);
                                multmp := op1 * op2;
-                               op3_next(CBITS-1) <= multmp((2*CBITS)-1);
                                op3_next((CBITS-2) downto 0) <= multmp((CBITS-2) downto 0);
-                               done_intern <= '1';
+                               op3_next(CBITS-1) <= mulsign;
+
+                               if mulsign = '1' then
+                                       multmp2 := not (multmp + 1);
+                               else
+                                       multmp2 := multmp;
+                               end if;
+                               -- overflow?
+                               if(multmp2((2*CBITS)-2 downto (CBITS-1)) > 0) then
+                                       error_intern <= '1';
+                               else
+                                       done_intern <= '1';
+                               end if;
+
                        when SDIV =>
                                -- division implementiert nach ~hwmod/doc/division.pdf
-                               if op2 = to_signed(0,CBITS) then
-                                       -- TODO: err out signal
-                                       done_intern <= '1';
+                               if ((op1 = x"80000000" and op2 = to_signed(-1, CBITS)) or op2 = to_signed(0, CBITS)) then
+                                       error_intern <= '1';
                                else
                                        -- sign check
                                        op1_var := op1;
@@ -196,8 +238,11 @@ begin
                        when SDIV_DONE =>
                                op3_next <= quo_int;
                                done_intern <= '1';
-                       when SDONE =>
+                       when SDONE | SERROR =>
                                calc_done_next <= '1';
+                               if (state_int = SERROR) then
+                                       calc_error_next <= '1';
+                               end if;
                                op3_next <= op3_int;
                end case;
        end process;