op1 : in csigned;
op2 : in csigned;
op3 : out csigned;
+ opM : out csigned;
do_calc : in std_logic;
calc_done : out std_logic;
calc_error : out std_logic
type ALU_STATE is (SIDLE, SADD, SSUB, SMUL, SDIV, SDIV_CALC, SDIV_DONE,
SDONE, SERROR);
signal state_int, state_next : ALU_STATE;
- signal done_intern, error_intern, div_calc_done, div_go_calc : std_logic;
- signal op3_int, op3_next : csigned;
+ signal done_intern, error_intern : std_logic;
+ signal div_calc_done_int : std_logic;
+ signal div_calc_done2_int : std_logic;
+ signal div_go_calc_int : std_logic;
+ signal op3_int, op3_next, opM_int, opM_next : csigned;
signal calc_done_int, calc_done_next : std_logic;
signal calc_error_int, calc_error_next : std_logic;
-- signale fuer division
- signal dividend_msb_int, dividend_msb_next, laengediv_int, laengediv_next : natural;
+ signal dividend_msb_int, dividend_msb_next, laengediv_int, laengediv_next : divinteger;
signal quo_int, quo_next, aktdiv_int, aktdiv_int_next, op1_int, op1_next, op2_int, op2_next : csigned;
signal sign_int, sign_next : std_logic;
begin
op3 <= op3_int;
+ opM <= opM_int;
calc_done <= calc_done_int;
calc_error <= calc_error_int;
if sys_res_n = '0' then
state_int <= SIDLE;
op3_int <= (others => '0');
+ opM_int <= (others => '0');
calc_done_int <= '0';
calc_error_int <= '0';
--div
elsif rising_edge(sys_clk) then
state_int <= state_next;
op3_int <= op3_next;
+ opM_int <= opM_next;
calc_done_int <= calc_done_next;
calc_error_int <= calc_error_next;
-- div
-- next state
process(state_int, opcode, done_intern, error_intern, do_calc,
- div_calc_done, div_go_calc)
+ div_calc_done_int, div_calc_done2_int, div_go_calc_int)
begin
-- set a default value for next state
state_next <= state_int;
state_next <= SERROR;
end if;
when SDIV =>
- if div_go_calc = '1' then
+ if div_go_calc_int = '1' then
state_next <= SDIV_CALC;
end if;
+ if div_calc_done2_int = '1' then
+ state_next <= SDIV_DONE;
+ end if;
if error_intern = '1' then
state_next <= SERROR;
end if;
when SDIV_CALC =>
- if div_calc_done = '1' then
+ if div_calc_done_int = '1' then
state_next <= SDIV_DONE;
end if;
when SDONE | SERROR =>
end process;
-- output
- process(state_int, op1, op2, dividend_msb_int, laengediv_int, quo_int, aktdiv_int, sign_int, op1_int, op2_int, op3_int)
+ process(state_int, op1, op2, dividend_msb_int, laengediv_int, quo_int,
+ aktdiv_int, sign_int, op1_int, op2_int, op3_int, opM_int)
variable multmp, multmp2 : signed(((2*CBITS)-1) downto 0);
variable mulsign : std_logic;
variable tmp : csigned;
-- vars fuer div
- variable laengediv_var, dividend_msb_var : natural;
+ variable laengediv_var, dividend_msb_var, divtmp : divinteger;
variable aktdiv_int_var, quo_var, op1_var, op2_var : csigned;
begin
calc_done_next <= '0';
calc_error_next <= '0';
- div_calc_done <= '0';
- div_go_calc <= '0';
+ div_calc_done_int <= '0';
+ div_calc_done2_int <= '0';
+ div_go_calc_int <= '0';
done_intern <= '0';
error_intern <= '0';
-- default fuer div
dividend_msb_next <= 0;
laengediv_next <= 0;
quo_next <= (others => '0');
- aktdiv_int_next <= (others => '0');
+ aktdiv_int_next <= aktdiv_int;
op1_next <= (others => '0');
op2_next <= (others => '0');
sign_next <= '0';
op3_next <= op3_int;
+ opM_next <= opM_int;
case state_int is
when SIDLE =>
- null;
+ opM_next <= (others => '0');
+ aktdiv_int_next <= (others => '0');
when SADD =>
tmp := op1 + op2;
op3_next <= tmp;
aktdiv_int_next <= op1_var srl (dividend_msb_var - laengediv_var + 1);
- div_go_calc <= '1';
- dividend_msb_next <= dividend_msb_var;
- laengediv_next <= laengediv_var;
- quo_next <= (others => '0');
- op1_next <= op1_var;
- op2_next <= op2_var;
- sign_next <= op1(CBITS-1) xor op2(CBITS-1);
+ -- anmerkung: xst (xilinx) kann folgende zeile nicht uebersetzen
+ -- > if op1 = to_signed(-2147483648, CBITS) then
+ -- darum folgende schreibweise ->
+ if op1 = x"80000000" then
+ -- so ziemlich das boeseste was passieren kann
+ div_calc_done2_int <= '1';
+ quo_next <= to_signed(-214748364,CBITS);
+ aktdiv_int_next <= to_signed(8,CBITS);
+ elsif (op1_var < op2_var) then
+ div_calc_done2_int <= '1';
+ quo_next <= to_signed(0,CBITS);
+ aktdiv_int_next <= op1_var;
+ else
+ div_go_calc_int <= '1';
+ dividend_msb_next <= dividend_msb_var;
+ laengediv_next <= laengediv_var;
+ quo_next <= (others => '0');
+ op1_next <= op1_var;
+ op2_next <= op2_var;
+ sign_next <= op1(CBITS-1) xor op2(CBITS-1);
+ end if;
end if;
when SDIV_CALC =>
- if (dividend_msb_int - laengediv_int + 1) > 0 then
+ divtmp := dividend_msb_int - laengediv_int + 1;
+
+ if divtmp > 0 then
aktdiv_int_var := aktdiv_int sll 1;
- aktdiv_int_var(0) := op1_int(dividend_msb_int - laengediv_int);
+ aktdiv_int_var(0) := op1_int(divtmp - 1);
quo_var := quo_int sll 1;
if aktdiv_int_var >= op2_int then
else
quo_next <= quo_int;
end if;
- div_calc_done <= '1';
+ div_calc_done_int <= '1';
end if;
when SDIV_DONE =>
op3_next <= quo_int;
+ opM_next <= aktdiv_int;
done_intern <= '1';
when SDONE | SERROR =>
calc_done_next <= '1';
projects / hwmod.git / blobdiff