- when SADD | SSUB | SMUL | SDIV | SDIV_CALC =>
- case state_int is
- when SDIV =>
- if div_go_calc_int = '1' then
- state_next <= SDIV_CALC;
- end if;
- when others => null;
- end case;
- if done_intern = '1' then
- state_next <= SDONE;
- end if;
- if error_intern = '1' then
- state_next <= SERROR;
- end if;
- when SDONE | SERROR =>
- if do_calc = '0' then
- state_next <= SIDLE;
- end if;
- end case;
- end process;
-
- -- output
- process(state_int, op1, op2, dividend_msb_int, laengediv_int, quo_int,
- aktdiv_int, sign_int, op1_int, op2_int, op3_int, opM_int)
- variable multmp, multmp2 : signed(((2*CBITS)-1) downto 0);
- variable mulsign : std_logic;
- variable tmp : csigned;
- -- vars fuer div
- variable laengediv_var, dividend_msb_var, divtmp : divinteger;
- variable aktdiv_int_var, quo_var, op1_var, op2_var : csigned;
- begin
- calc_done_next <= '0';
- calc_error_next <= '0';
- div_go_calc_int <= '0';
- done_intern <= '0';
- error_intern <= '0';
- -- default fuer div
- dividend_msb_next <= (others => '0');
- laengediv_next <= (others => '0');
- quo_next <= (others => '0');
- aktdiv_int_next <= aktdiv_int;
- op1_next <= (others => '0');
- op2_next <= (others => '0');
- sign_next <= '0';
- op3_next <= op3_int;
- opM_next <= opM_int;
-
- case state_int is
- when SIDLE =>
- opM_next <= (others => '0');
- aktdiv_int_next <= (others => '0');