uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / src / Makefile

diff --git a/src/Makefile b/src/Makefile
index 730c2722d97a79fd5aa3e6faf478e4a6f549ddd6..32002123835b318aeea52d56a134d1a5f2be5f19 100644 (file)
--- a/src/Makefile
+++ b/src/Makefile
@@ -1,4 +1,5 @@
 SHELL := bash
+VPATH := .:ps2:textmode_vga:textmode_vga/mjl_stratix
 
 MPWD := $(shell pwd)
 D_BEHSIM := $(MPWD)/../sim/beh
@@ -12,24 +13,53 @@ QUOPT := --read_settings_files=on --write_settings_files=off calc -c calc
 HN := $(shell hostname)
 TILABHOSTS := $(shell echo ti{1..9}) apps1
 
+ifeq ($(findstring $(HN), $(TILABHOSTS)),$(HN))
+# die option 's' geht nicht... :(
+COVERVCOM := -cover bcet
+COVERVSIM := -coverage
+else
+COVERVCOM :=
+COVERVSIM :=
+endif
+
+ifeq ($(findstring $(HN), $(TILABHOSTS)),$(HN))
+QUMACRO := unset LS_COLORS; cd $(QUARTUS); export LD_LIBRARY_PATH=/opt/quartus/quartus/linux64; export LM_LICENSE_FILE=26888@quartus; 
+else
+QUMACRO := unset LS_COLORS; cd $(QUARTUS);
+endif
+
 WORK := work
 
+# o source files der module
 # o reihenfolge ist wichtig
 # o keine testbechnes hier angeben
-BEH_IFILES = gen_pkg alu
+SRCFILES := alu parser scanner display sp_ram history uart_tx uart_rx pc_communication
+
+# o files der packages
+# o keine testbechnes hier angeben
+PKGFILES = math_pkg gen_pkg
+PKGFILES += textmode_vga/textmode_vga_platform_dependent_pkg
+PKGFILES += textmode_vga/textmode_vga_pkg
+PKGFILES += textmode_vga/font_pkg
+PKGFILES += textmode_vga/textmode_vga_component_pkg
+
+BEH_IFILES = $(PKGFILES) $(SRCFILES)
 BEH_IFILES := $(strip $(BEH_IFILES))
 
-# o keine testbenches hier angeben
-# o beachte, dass sich viele files schon in dem VHO file befinden -- es muessen eigentlich nur
-#   abhaengigkeiten fuer die testbenches angegeben werden
-POST_IFILES = gen_pkg
+POST_IFILES = $(PKGFILES)
 POST_IFILES := $(strip $(POST_IFILES))
 
+POST_SRC = $(SRCFILES)
+
+
 #virtuelle targets fuer behsim: weil wir sowas wie ein objectfile von vcom nicht bekommen. bessere ideen sind willkommen
-BEH_VTARGETS := $(foreach n, $(BEH_IFILES), $(D_BEHSIM)/$(WORK)/$(n)/_primary.dat)
+BEH_VTARGETS := $(foreach n, $(notdir $(BEH_IFILES)), $(D_BEHSIM)/$(WORK)/$(n)/_primary.dat)
+
+#virtuelle targets fuer packagefiles der postsim
+POST_VTARGETS := $(foreach n, $(notdir $(POST_IFILES)), $(D_POSTSIM)/$(WORK)/$(n)/_primary.dat)
 
-#virtuelle targets fuer postsim
-POST_VTARGETS := $(foreach n, $(POST_IFILES), $(D_POSTSIM)/$(WORK)/$(n)/_primary.dat)
+#virtuelle targets fuer sourcefiles der postsim
+POST_SRC_VTARGETS := $(foreach n, $(POST_SRC), $(n).vhd)
 
 
 all: behsim
@@ -47,15 +77,15 @@ $(D_BEHSIM)/modelsim.ini:
 
 $(D_BEHSIM)/$(WORK)/%/_primary.dat: %.vhd $(D_BEHSIM)/modelsim.ini
        @echo " CC    $<"
-       @cd $(D_BEHSIM); \
-       vcom -work $(WORK) $(MPWD)/$<
+       cd $(D_BEHSIM); \
+       vcom $(COVERVCOM) -work $(WORK) $(MPWD)/$<
 
 beh_%: $(D_BEHSIM)/$(WORK)/beh_%_tb/_primary.dat beh_%_tb.do behsim
        cd $(D_BEHSIM); \
-       vsim "work.$@_tb(sim)" -f /dev/null -do $(MPWD)/$@_tb.do
+       vsim $(COVERVSIM) "work.$@_tb(sim)" -f /dev/null -do $(MPWD)/$@_tb.do
 
 #postsim
-postsim: $(POST_VHO) $(D_POSTSIM)/modelsim.ini $(POST_VTARGETS)
+postsim: post_alu
 
 $(D_POSTSIM)/modelsim.ini:
        @echo " INIT for post-layout simulation"
@@ -64,48 +94,39 @@ $(D_POSTSIM)/modelsim.ini:
        vlib work > /dev/null ; \
        vmap work work > /dev/null ;
 
-$(D_POSTSIM)/$(WORK)/%/_primary.dat: %.vhd $(D_POSTSIM)/modelsim.ini
+$(D_POSTSIM)/$(WORK)/%/_primary.dat: %.vhd
        @echo " CC    $<"
        @cd $(D_POSTSIM); \
        vcom -work $(WORK) $(MPWD)/$<
 
-post_%: $(D_POSTSIM)/$(WORK)/post_%_tb/_primary.dat post_%_tb.do postsim $(POST_SDO)
+post_%: quartus_gen_% post_%_tb.do $(D_POSTSIM)/$(WORK)/post_%_tb/_primary.dat
        cd $(D_POSTSIM); \
        vsim "work.$@_tb(sim)" -sdftyp /$(POST_SDO_INST)=$(POST_SDO) -f /dev/null -do $(MPWD)/$@_tb.do
 
-$(QUARTUS):
+quartus_gen_%: ../quartus/project_%.tcl $(D_POSTSIM)/modelsim.ini $(POST_VTARGETS) $(POST_SRC_VTARGETS)
        @echo -n " Quartus  generate project"
 ifeq ($(findstring $(HN), $(TILABHOSTS)),$(HN))
-       @echo "(@tilab)"
-       @cd ../quartus; ./linux_tilab.sh
+       @echo "(@tilab): $<"
+       @cd ../quartus; rm -Rf calc; ./linux_tilab.sh $<
 else
-       @echo "(not @ tilab)"
-       @cd ../quartus; ./linux_web.sh
+       @echo "(not @ tilab): $<"
+       @cd ../quartus; rm -Rf calc; ./linux_web.sh $<
 endif
-
-#TODO: more targets plz...
-$(POST_VHO) $(POST_SDO): $(QUARTUS) postsim
        @echo " Quartus  analysis & synthesis"
-       @unset LS_COLORS; cd $(QUARTUS); \
-       quartus_map $(QUOPT)
+       @$(QUMACRO) quartus_map $(QUOPT)
        @echo " Quartus  fitter"
-       @unset LS_COLORS; cd $(QUARTUS); \
-       quartus_fit $(QUOPT)
+       @$(QUMACRO) quartus_fit $(QUOPT)
        @echo " Quartus  assembler"
-       @unset LS_COLORS; cd $(QUARTUS); \
-       quartus_asm $(QUOPT)
+       @$(QUMACRO) quartus_asm $(QUOPT)
        @echo " Quartus  timing analyzer"
-       @unset LS_COLORS; cd $(QUARTUS); \
-       quartus_tan $(QUOPT) --timing_analysis_only
+       @$(QUMACRO) quartus_tan $(QUOPT) --timing_analysis_only
        @echo " Quartus  EDA netlist writer"
-       @unset LS_COLORS; cd $(QUARTUS); \
-       quartus_eda $(QUOPT)
-       #not nice atm :/
+       @$(QUMACRO) quartus_eda $(QUOPT)
        @echo " CC    $(POST_VHO)"
        @cd $(D_POSTSIM); \
        vcom -work $(WORK) $(POST_VHO)
 
 .PHONY: clean
 clean:
-       rm -Rf $(D_BEHSIM) $(D_POSTSIM) $(QUARTUS)
+       rm -Rf $(D_BEHSIM) $(D_POSTSIM)