uart_rx: ein prozessmodell. spart weitere 3 logic elements :P

[hwmod.git] / spartan3e / spartan3e.ucf

diff --git a/spartan3e/spartan3e.ucf b/spartan3e/spartan3e.ucf
index 5e47e3b741cf984b7705cdf9ef52748e145cb132..d31e9759d6ba70959a58a69599ed70eee9b834ca 100644 (file)
--- a/spartan3e/spartan3e.ucf
+++ b/spartan3e/spartan3e.ucf
@@ -13,7 +13,7 @@
 #NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
 #NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
 NET "sys_res" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
-#NET "BTN_WEST" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
+NET "btn_a" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
 # ==== Clock inputs (CLK) ====
 NET "CLK_50MHZ" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
 # Define clock period for 50 MHz oscillator (40%/60% duty-cycle)