VHDL_DIR := ../src
PROJ_VHDL = alu.vhd \
textmode_vga/spartan3e_starterkit/textmode_vga_platform_dependent_pkg.vhd \
+ clk_vga_s3e.vhd \
calc_s3e.vhd \
- dcm_s3e.vhd \
display.vhd \
history.vhd \
math_pkg.vhd \
generated/$(NAME).bit: bitfile
+jtag: generated/$(NAME).bit
+ impact -batch ISE_scripts/loadjtag.cmds
+
mcs: generated/$(NAME).bit
impact -batch ISE_scripts/makeprom.cmds