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uart_rx: ein prozessmodell. spart weitere 3 logic elements :P
[hwmod.git]
/
.gitignore
diff --git
a/.gitignore
b/.gitignore
index d4daef8cff14d99e263b5999a830ab6b8e451376..34721068c010f3c28fd6a439735a6bb452f8c4b3 100644
(file)
--- a/
.gitignore
+++ b/
.gitignore
@@
-13,7
+13,8
@@
spec/*.png
*.ppk
#sim
-sim/
+sim/post
+sim/beh
#modelsim
src/transcript
@@
-26,3
+27,6
@@
quartus/project_tilab.tcl
#stuff
tags
+
+#abgabe
+abgabe_g20_*.zip